Abstract: An error detection and recovery apparatus for monitoring, and recovering from, errors in a system having one or more logic units. An error detector detects errors in the logic units, and provides error signals in response. A first error processor receives selected error signals, and performs system recovery according to the particular error signals present. A second error processor receives other selected error signals, and performs error recovery of the logic unit only, without affecting the rest of the system. The second error processor performs error recovery through real-time execution of error recovery routines at the logic unit. A selector is provided to determine which of the error signals are provided to the first and second error processors. A memory stack having multiple memory locations is also provided to store bus information captured from a bus, which can be used by the second error processor in its error recovery.