Abstract: A method includes setting a contention scheme for an asynchronous bus such that the contention delay of isochronous transactions on the asynchronous bus is bounded. A first device is coupled to the asynchronous bus to receive an isochronous transaction from an isochronous device and output the isochronous transaction to the asynchronous bus. A second device is coupled to the asynchronous bus to receive the isochronous transaction from the asynchronous bus and output the isochronous transaction to a third device.
Abstract: A method includes producing a control voltage signal that exceeds a rated maximum control voltage signal level for a switch, and limiting the control voltage signal applied to the switch to no greater than the rated maximum control voltage signal level.
Abstract: A numerical processing method on a computer system in which an instruction having at least one operand and a type control is retrieved, and the operand is converted to a precision specified by the type control. The instruction is executed in the precision specified by the type control to obtain a result, and when the destination precision differs from the precision specified by the type control, the result is converted to the destination precision using a second instruction.
Abstract: In a microprocessor, an instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and forwards the dependency information to the dependency matrix 36 in the form of a dependency vector 40. The dependency matrix 36 periodically determines whether any of the instructions contained in the waiting buffer 34 are ready to be executed, that is, no dependencies exist for that instruction. As each instruction is dispatched for execution from the waiting buffer 34, the dependency vector 40 for all dependent instructions is cleared for subsequent execution. In this manner, an out-of-order processing scheme is implemented that efficiently accounts for data dependency between processed instructions.
Type:
Grant
Filed:
January 8, 1997
Date of Patent:
May 16, 2000
Assignee:
Intel Corporation
Inventors:
Nazar Zaidi, Gary Hammond, Ken Shoemaker, Jeff Baxter
Abstract: A method and system for adding device entries to a device tree is disclosed. When the computer system detects the connection of a device, the computer system searches a device tree to determine if the device is being connected for the first time. If so, a device entry for the device, including a device type and at least one device function, is added to the device tree. Using the device type and at least one device function, the system searches a match tree to identify at least one first sequence of instructions to execute when the device is connected for the first time. The first sequence of instructions modifies the device entry to associate at least one software category with the device. The first sequence of instructions may: (1) modify the device entry to include at least one software component to be notified when the device is connected; and/or (2) modify the device entry to associate with each software category at least one software component to be used with the device.