Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
Type:
Grant
Filed:
August 31, 2000
Date of Patent:
June 27, 2006
Assignee:
Micron Technology, Inc.
Inventors:
Randhir P. S. Thakur, Ravi Iyer, Howard Rhodes