Abstract: A substantial savings in computational time is realized by the use of plural parallel processing elements, each element having vector processing capabilities. The plurality of vector processor elements will concurrently perform calculations for a number of a groups of equations. The system determines the values of recurrent variables in a set of equations which define a linear recurrence in any order under program control by dividing said set of equations into groups of consecutive equations, determining temporary (or partial) values of the recurrence variables for each group with those recurrence variables which are derived in the equation in the next preceding group being set to zero, determining for each equation values of coefficients for those recurrence variables which were set to zero, and determining the final values of previously unsolved recurrence variables.

Abstract: The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability.

Abstract: A method for fabricating bipolar and CMOS devices in integrated circuits using W as a local interconnect and via landing pad for bipolar and CMOS devices. The method includes the forming of an oxide/silicon bilayer above a local interconnect of tungsten/titanium wherein the oxide is patterned as a mask for the silicon/tungsten/titanium reactive ion etch, and the silicon layer above the tungsten/titanium layer is used as an etch stop for a via etch. The silicon layer is then reacted and converted to titanium silicide after the via etch to provide a low resistance path in the via from the local interconnect in a self aligned manner.