Abstract: A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.

Abstract: A method for forming a metallic reflecting layer in a semiconductor photodiode including a CMOS photodiode to enhance the sensitivity by filling a trench formed in the isolation next to the depletion region of the semiconductor photodiode with high reflectivity metal. The metal filled in the trench is used as a metallic reflecting layer to increase the number of photons reaching the depletion region by reflecting part of the aslope incident photons. An insulator is formed on the top of the metallic reflecting layer to electrically insulate the metallic reflecting layer from other conducting device formed by the follow-up process.

Abstract: A method for forming a metal plug is provided. The method is used to form a metal plug without a hole on a glue/barrier layer within a trench when the glue/barrier layer has been formed for a while. A substrate with a trench therein and a glue/barrier layer formed conformal to the profile of the substrate is provided. A post-treatment is performed on the glue/barrier layer to prevent moisture absorption and to make the glue/barrier become dense. The post-treatment comprises a plasma treatment or a deep UV plus laser treatment. After performing the post-treatment step, a metal layer is formed on the glue/barrier layer at least to fill in the trench. The metal layer other than that filling the trench is removed to form a metal plug.

Abstract: A fabrication method for shallow trench isolation (STI) is briefly described as follows. A substrate is provided with a patterned mask layer and pad oxide layer formed thereon, so that a first opening, which exposes a part of the substrate, is formed. A shallow trench is then formed in the substrate, followed by filling the shallow trench with a first insulating layer, wherein the surface of the first insulating layer is lower than the surface of the substrate, and a part of the substrate forming the sidewall of the shallow trench is exposed. A part of the mask layer and pad oxide layer is removed to enlarge the first opening, so that a second opening, which exposes a part of the substrate, is formed. A doped region is formed on the exposed part of the substrate, while the second opening and the shallow trench are filled with a second insulating layer. Finally, the mask layer and the pad oxide layer are removed in sequence to complete the manufacture of the STI.

Abstract: A method of manufacturing multiple metallic layered embedded ROM. A substrate has a memory cell region and a peripheral circuit region. A first gate and a first source/drain region are formed in the memory cell region. A second gate and a second source/drain region are formed in the peripheral circuit region. A first dielectric layer is formed over the substrate. A first contact is formed in the first dielectric layer in the periphery circuit region. A first patterned metallic layer that couple electrically with the first contact is formed in the peripheral circuit region. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer in the memory cell region is removed to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region. A via hole is formed in the second dielectric layer in the peripheral circuit region and a second contact opening is formed in the first dielectric layer in the memory cell region.

Abstract: A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.

Abstract: A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the pad oxide layer and the substrate is removed to form a trench in the substrate. Insulation material is deposited into the trench to form an insulation plug. The hard mask layer is removed to expose the sidewalls of the insulation plug. Spacers are formed on the exposed sidewalls of the insulation plug. Ions are implanted into the substrate. The pad oxide layer, the spacers and a portion of the insulation plug are removed. Finally, a gate oxide layer thicker in region around the edge of the insulation plug is formed over the substrate by oxidation.