Abstract: A transformer with an associated heat-dissipating plastic element is provided. The transformer includes a hollow main body, a core, a coil and a heat-dissipating plastic element. The core is installed inside the hollow main body while the coil wraps around the core. The heat-dissipating plastic element is also installed inside the hollow main body. The heat-dissipating plastic element encloses the core and the coil. Alternatively, the heat-dissipating plastic element encloses the hollow main body, the core and the coil so that heat generated by the coil may be directly conducted away to the exterior through the heat-dissipating plastic element.

Abstract: A method for manufacturing low cost electroluminescent (EL) illuminated membrane switches is disclosed. The method includes the first step of die cutting, embossing or chemically etching the metal foil surface of a metal foil bonded, light transmitting flexible electrical insulation to simultaneously form one or more front capacitive electrodes, membrane switch contacts and electrical shunt, electrical distribution means and electrical terminations that together comprise a flexible printed circuit panel. This continuous flexible printed circuit substrate is then coupled to a precisely positioned indexing system. Next, the front metal foil capacitive electrodes are coated with a light transmissive electrically conductive layer.

Abstract: A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal layer. Then, a post-etching cleaning step is carried out to clean the dual damascene opening, and there are two types of cleaning methods. The first method uses a fluorine-based solvent to clean the dual damascene opening. An alternative cleaning method uses a hydrogen peroxide based solvent at a high temperature, followed by a hydrofluoric acid solvent cleaning step. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.

Abstract: A tape-out system of a mask tooling network for multiple supply chain. The tape-out system includes an integrated circuit (IC) designer computer, a design service computer, and a mask house computer; wherein the IC designer computer, the design service computer and the mask house computer are the multi-users for the tape-out system. A network connects the IC designer computer, the design service computer and the mask house computer. A device design data and a product mask data are provided through the network from the IC designer computer to the design service computer. The device design data and the product mask data undergo a processing step and a summarizing step, so that a product mask tooling data is obtained, which is then transmitted through the network to the mark house computer and the IC designer computer. The mask house computer fabricates a mask in accordance with the product mask tooling data.

Abstract: A fabrication method for a low dielectric constant (k) material layer is described. A high molecular weight material layer is formed on a substrate. The high molecular weight material layer is then cured. A bonding material layer is formed on the high molecular weight material layer, wherein a major component in the bonding material layer is an organic compound, wherein the organic compound has a silicon-containing moiety and an unsaturated hydrocarbon moiety. The bonding material layer is further cured, allowing the organic silicon compound to cross-link within the high molecular weight material layer to form a high molecular weight material layer with a silicon rich surface. Moreover, the curing for the high molecular weight material layer and for the bonding material layer can conduct concurrently.

Abstract: A method of manufacturing a low-leakage, high-performance device. A substrate having a gate electrode thereon is provided. A lightly doped, high-energy implantation is conducted to form a lightly doped source/drain terminal in the substrate. An offset spacer is formed on each sidewall of the gate electrode. A heavily doped implantation is conducted to form a heavily doped source/drain terminal in the substrate. The heavily doped source/drain terminal has a depth smaller than the lightly doped source/drain terminal. A protective spacer structure is formed on each sidewall of the gate electrode. A deep-penetration source/drain implantation is carried out to form a deep source/drain terminal in the substrate.

Abstract: An electron beam photolithographic process for patterning an insulation layer over a substrate. A conductive photoresist layer having a conjugate structure is formed over the insulation layer. An electron beam photolithographic process is conducted using a photomask so that the pattern on the photomask is transferred to the conductive photoresist layer.

Abstract: A radiation detection device for locally detecting radiation of RF energy emissions from close proximity direct line-of-sight electromagnetic fields emitted by a wireless transmit/receive electronic equipment antenna 22 or body 21 such as a cellular telephone, in miniature/planar design form with suitable embedding form-factoring fashioned arrangement capability joined with radiation shielding devices. Said radiation detection device operates without prerequisite need for a battery or external power source, operationally self-powered by the embodiments of this invention when exposed to electromagnetic field radiation of predetermined thresholding energy level setting for the user's own personal alerting verification and assessment means of suitable predetermined radiation detection measurement tester coupling to radiation shielding devices to encompass an overall shield effectiveness system solution in real-time monitoring response fashion operation.

Abstract: A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.

Abstract: An optical proximity correction method. Assist features, such as scattering bars, are added to a main pattern to be transferred. Calculations are performed on the entire two-dimensional original pattern using model-based optical proximity correction. A series of features are added according to the specific reference indexes of the coordinate system. The original pattern is altered to form a corrected pattern. The process of calculation and correction, however, does not include the scattering bars.

Abstract: A static random access memory manufacturing method. A substrate having a gate oxide layer and a first conducting layer is defined to form a buried contact window opening. A second conducting layer is formed upon the substrate with a recess structure at the region of the buried contact opening. A buried contact window is formed in the substrate under the buried contact window opening. A protective layer is formed upon the substrate and fills the recess. A portion of the protective layer is removed, and a patterned photoresist layer is formed upon the substrate. Using the photoresist as a mask, the first and second conducting layer are etched to form a gate electrode and an interconnect. The patterned photoresist layer is removed. The protective layer can be removed or retained. An implantation procedure is performed, thereby forming a source/drain, thereby connecting the source/drain and the contact window.

Abstract: A structure of a DRAM and a manufacturing process therefor, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed. A plurality of bit line contacts and a plurality of node contacts are formed in electric contact with the source/drain regions. A first patterned insulating layer is formed on the substrate, in which a plurality of openings are formed in the insulating layer to expose the bit line contacts. The substrate is covered with a first conductive layer and a second insulating layer in sequence. The second insulating layer, the first conductive layer and the first insulating layer are patterned in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connecting to the bit contacts, exposing the node contacts. As a result, the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines.

Abstract: A method of removing silicon carbide. A silicon wafer is used as a dummy wafer for inspecting the properties of a silicon carbide thin film which is to be formed thereover. A silicon nitride layer with a thickness larger than about 1000 angstroms is formed on the dummy wafer as a base layer of the silicon carbid thin film. The silicon carbide thin film is then formed on the base layer. The property inspection of the silicon carbide thin film is performed. After the properties inspection, the silicon carbide is stripped using a high density hydrogen plasma. After the step of high density hydrogen plasma, if the remaining silicon nitride layer is thicker than about 500 angstroms, the remaining silicon nitride layer can be used as the base layer again for forming and inspecting the properties of the silicon carbide thin film.

Abstract: A method of forming a dynamic random access memory. A substrate having a memory cell region and a logic circuit region is provided. The substrate also has a first dielectric layer thereon. The first dielectric layer in the memory cell region has a bit line and a node contact while the first dielectric layer in the logic circuit region has a first metallic interconnect. An intermediate dielectric layer is formed over the first dielectric layer such that the intermediate dielectric layer in the logic circuit region has a second metallic interconnect that connects electrically with the first metallic interconnect. A capacitor is formed in the intermediate dielectric layer within the memory cell region. A second dielectric layer is formed over the substrate. A third metallic interconnect is formed in the second dielectric layer such that the third metallic interconnect and the second metallic interconnect are electrically connected.

Abstract: A method for stripping a low dielectric film with a high carbon content from silicon monitor chip. The silicon monitor chip is placed inside a plasma-enhanced chemical vapor deposition chamber and the surface is treated with oxygen plasma to form a silicon-rich oxide layer. A high-carbon-content low dielectric film is formed over the silicon-rich oxide for film quality inspection. After the film inspection, the silicon monitor chip is immersed in a solution containing ammonium hydroxide and hydrogen peroxide so that the surface of the high-carbon-content dielectric film is transformed from hydrophobic to hydrophilic. Hence, wetting capacity of subsequently applied hydrofluoric acid solution is enhanced. Finally, the silicon monitor chip is immersed in a hydrofluoric acid solution for stripping away the low dielectric film.

Abstract: A method for fabricating an interconnect structure by a dual damascene process is described, in which a first low dielectric constant material is formed on a substrate, followed by forming a gradient silicon oxy-nitride layer on the first low dielectric constant. A second low dielectric constant layer is further formed on the gradient silicon oxy-nitride layer. A trench line is then formed in the second low dielectric constant material using the gradient silicon oxy-nitride layer as an etch-stop, followed by forming a via under the trench line.

Abstract: A method of protecting gate oxide. A chip having a gate thereon is provided. The gate structure comprises a gate oxide layer and a gate electrode. The gate is covered by a dielectric layer. A protection layer is formed on the dielectric layer. The protection layer is pattern to remain a part of the protection layer aligned over the gate.

Abstract: A method of manufacturing a flash memory having a dual floating gate structure. A source/drain region is formed in a substrate. A first conductive layer is formed on the substrate and between the source/drain region. A first dielectric layer is located between the substrate and the first conductive layer. A floating gate mask is formed on the substrate and the first conductive layer to expose a portion of the first conductive layer. The portion of the first conductive layer and a portion of the first dielectric layer beneath the exposed conductive layer are removed. The floating gate mask is removed. A conformal second dielectric layer and a second conductive layer are formed over the substrate in sequence. The second conductive layer and the second dielectric layer are formed to respectively form a control gate and a third dielectric layer.

Abstract: A method for increasing gate surface area for depositing silicide material. A silicon substrate having device isolation structures therein is provided. A stack of sacrificial layers comprising a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer on top is formed over the silicon substrate. A gate opening that exposes a portion of the substrate is formed in the stack of sacrificial layers. A portion of the second sacrificial layer exposed by the gate opening is next removed to form a side opening on each side of the gate opening. The gate opening together with the horizontal side opening form a cross-shaped hollow space. A gate oxide layer is formed at the bottom of the gate opening. Polysilicon material is deposited to fill the gate opening and the side openings, thereby forming a cross-shaped gate polysilicon layer. The third, the second and the first sacrificial layers are removed. A metal silicide layer is formed over the gate polysilicon layer.

Abstract: A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.