Abstract: A method for stripping a low dielectric film with a high carbon content from silicon monitor chip. The silicon monitor chip is placed inside a plasma-enhanced chemical vapor deposition chamber and the surface is treated with oxygen plasma to form a silicon-rich oxide layer. A high-carbon-content low dielectric film is formed over the silicon-rich oxide for film quality inspection. After the film inspection, the silicon monitor chip is immersed in a solution containing ammonium hydroxide and hydrogen peroxide so that the surface of the high-carbon-content dielectric film is transformed from hydrophobic to hydrophilic. Hence, wetting capacity of subsequently applied hydrofluoric acid solution is enhanced. Finally, the silicon monitor chip is immersed in a hydrofluoric acid solution for stripping away the low dielectric film.

Abstract: A method for fabricating an interconnect structure by a dual damascene process is described, in which a first low dielectric constant material is formed on a substrate, followed by forming a gradient silicon oxy-nitride layer on the first low dielectric constant. A second low dielectric constant layer is further formed on the gradient silicon oxy-nitride layer. A trench line is then formed in the second low dielectric constant material using the gradient silicon oxy-nitride layer as an etch-stop, followed by forming a via under the trench line.

Abstract: A method of protecting gate oxide. A chip having a gate thereon is provided. The gate structure comprises a gate oxide layer and a gate electrode. The gate is covered by a dielectric layer. A protection layer is formed on the dielectric layer. The protection layer is pattern to remain a part of the protection layer aligned over the gate.

Abstract: A method of manufacturing a flash memory having a dual floating gate structure. A source/drain region is formed in a substrate. A first conductive layer is formed on the substrate and between the source/drain region. A first dielectric layer is located between the substrate and the first conductive layer. A floating gate mask is formed on the substrate and the first conductive layer to expose a portion of the first conductive layer. The portion of the first conductive layer and a portion of the first dielectric layer beneath the exposed conductive layer are removed. The floating gate mask is removed. A conformal second dielectric layer and a second conductive layer are formed over the substrate in sequence. The second conductive layer and the second dielectric layer are formed to respectively form a control gate and a third dielectric layer.

Abstract: A method for increasing gate surface area for depositing silicide material. A silicon substrate having device isolation structures therein is provided. A stack of sacrificial layers comprising a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer on top is formed over the silicon substrate. A gate opening that exposes a portion of the substrate is formed in the stack of sacrificial layers. A portion of the second sacrificial layer exposed by the gate opening is next removed to form a side opening on each side of the gate opening. The gate opening together with the horizontal side opening form a cross-shaped hollow space. A gate oxide layer is formed at the bottom of the gate opening. Polysilicon material is deposited to fill the gate opening and the side openings, thereby forming a cross-shaped gate polysilicon layer. The third, the second and the first sacrificial layers are removed. A metal silicide layer is formed over the gate polysilicon layer.

Abstract: A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.

Abstract: A method to lower the parasitic capacitance is described, in which a low dielectric constant air-gap is formed in the dielectric layers at both sides of the gate to lower the parasitic capacitance present between the gate and the source/drain region. The air-gap is formed by forming spacers at both sides of the gate, followed by forming a first dielectric layer with its height lower than the top of the spacers. Thereafter, the spacers are removed by wet etching to form a hole with its top narrower than its bottom. A second dielectric layer is further formed, by a deposition technique with a weaker step coverage capability, to encapsulate the hole and to cover the substrate, wherein the encapsulated hole is the air-gap.

Abstract: A fabrication process for a polysilicon gate is described in which a silicon dioxide layer of various thicknesses is formed on the substrate and on the polysilicon gate with an overlying anti-reflection layer. The silicon dioxide layer is removed with enough silicon dioxide layer remaining to cover the sidewalls of the polysilicon gate and the silicon substrate before the removal of the anti-reflection layer. The sidewalls of the polysilicon gate and the silicon substrate are thus simultaneously protected during the removal of the anti-reflection layer.

Abstract: A method for fabricating a DRAM with a silicide layer formed on a gate of a MOS transistor in a memory region is provided. The method not only forms a first silicide layer on a first MOS transistor at the periphery region as a conventional structure but also forms a second silicide layer on a gate of a second MOS transistor, at the memory region. The second silicide layer is formed on a polysilicon layer before the polysilicon is patterned to form a gate so that the gate includes the second silicide layer on it top. An insulating layer is also formed over the substrate before the polysilicon is patterned so that the insulating layer serve as a mask when an interchangeable source/drain region of the second MOS transistor is formed.

Abstract: A method for forming a metal plug is provided. The method is used to form a metal plug without a hole on a glue/barrier layer within a trench when the glue/barrier layer has been formed for a while. A substrate with a trench therein and a glue/barrier layer formed conformal to the profile of the substrate is provided. A post-treatment is performed on the glue/barrier layer to prevent moisture absorption and to make the glue/barrier become dense. The post-treatment comprises a plasma treatment or a deep UV plus laser treatment. After performing the post-treatment step, a metal layer is formed on the glue/barrier layer at least to fill in the trench. The metal layer other than that filling the trench is removed to form a metal plug.

Abstract: A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.

Abstract: A multiple box case for housing audio equipment in both a transport and an operating mode is disclosed. An upper box has six latches extending downward to engage two continuous slider members fastened to a lower box to secure the case in the transport or closed mode. In an open or operating position, the upper box is cantilevered over the rear of the lower box and four of the six latches engage the two slider members in an operator preferred one of a plurality of continuously selectable positions. A safety stop bolt is installed in each slider member so as to preclude unstable positioning of the upper box.

Abstract: A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the pad oxide layer and the substrate is removed to form a trench in the substrate. Insulation material is deposited into the trench to form an insulation plug. The hard mask layer is removed to expose the sidewalls of the insulation plug. Spacers are formed on the exposed sidewalls of the insulation plug. Ions are implanted into the substrate. The pad oxide layer, the spacers and a portion of the insulation plug are removed. Finally, a gate oxide layer thicker in region around the edge of the insulation plug is formed over the substrate by oxidation.

Abstract: A method of fabricating a dynamic random-access memory (DRAM) device integrates a shallow trench isolation (STI) process and a storage node process into the fabrication of the DRAM device. With a bit line over capacitor (BOC) structure, the capacitor is laid out in parts of the shallow trench isolation structure to increase the surface area of the storage node by using the trench. During the fabrication of the capacitor, a stacked plug used to connect the bit line is formed. The stacked plug used as the interconnection in the circuit region is also formed. An insulating layer is formed to cover the capacitor, and an opening is formed therein to expose the stacked plug. A bit line and an interconnection are formed on the insulating layer to connect with a conducting layer which is located in the stacked plug and contacted with the source/drain regions.