Abstract: A generally planar shaped inductor is disclosed that is particularly adaptable for use in motion or position sensors. One inductor can function as a signal input unit and another as a pick up unit in an arrangement wherein both inductors are placed in a generally parallel juxtaposition for flux flow there between. A movable armature is located between the inductors to control the amount of flux transmission between inductors. The position of the armature relative to the inductors controls the output signal generated by the pickup inductor that are adapted to be converted into indications of displacements.

Abstract: Sensors, apparatus, and methods for measuring movements are disclosed. The sensors include input and output windings wound about a common location and an armature is equally positioned relative to both windings movable to vary inductance reactance of the sensor. The mass of the sensor and the ease of movements are such that flexible membranes, such as skin, can be monitored with insignificant interference. The sensor can be included in “Band-aid” bandage arrangement in which the bandage backing can be removed and held in place on skin by the bandage. A monitoring circuit, responsive to the changes in sensor impedance, provides indications of the detected movements. The monitoring circuit includes an arrangement for self-adjusting parameters so that the system can be automatically preset and continually reset. The monitoring circuit includes a power savings arrangement.

Abstract: A bandage type sensor arrangement wherein the sensor includes two parts movable with respect to each other, a carrier assembly is connected to the sensor parts for maintaining the sensor parts in place prior to use, and that is readily detachable for releasing the sensor parts while providing a connection of the sensor parts to a surface to be monitored. A cover is included as part of the carrier assembly to protect the operation of the sensor.

Abstract: A differential comparator with inputs switched and capacitively coupled to inverters which have capacitive cross-coupling feedback for a latching operation. The inverters also have direct switched feedback for autozeroing. The inputs further have a shorting switch between the input switches and the coupling capacitors for offset compensation. Complementary operation of the switches provides precharge and evaluation phases of operation. During precharge the inputs are applied to the input coupling capacitors and the inverters are autozeroed; during evaluation the inputs are transferred to the inverters through the coupling capacitors and the outputs feedback positively through the cross-coupling capacitors to latch the pair of inverters.

Abstract: A mechanism structure for decoupling prong and socket type electrical connections, particularly for circuit board cards and their connections to receptacle-connectors in chassis-like housings. In one embodiment, the decoupling structure comprises a plate, a rotatable rod supported by the plate, an actuating lever attached to one end of the rod, and a cam attached along the rod. In application, the lever is pushed or pulled causing the cam to apply a force separating the circuit board from the receptacle connection so as to reduce or avoid torsional forces when disconnecting the board from the receptacle.

Abstract: A sine/cosine generator with coarse and fine angles having compressed sine and cosine read only memories (ROMS) by use of symmetry of coarse angles about .pi./4 and, optionally, symmetry of fine angles about 0. The output of the ROMs directly feed multiplexers for utilization of the compressed storage. Addressing of complementary coarse angles is with one's complementing of the address and of complementary fine angles is with two's commplementing of the address. Fine sines and cosines are stored in recoded version for direct use in multipliers for computations using the sum of angles formulas.

Abstract: A semiconductor-on-insulator structure incorporating a layer of diamond material and method for preparing such. The structure comprises a layer containing diamond material and having a first surface. A layer of silicon nitride is formed on the first surface and a layer of semiconductor material is positioned over the silicon nitride layer. In one embodiment of the method there is provided a removable deposition surface. A layer of crystalline diamond material is formed on the deposition surface. A first surface of the diamond material is separated from the deposition surface. The structure is useful for formation of integrated circuits thereon.

Abstract: A recoding method of two or more bit groups to reduce the number of partial products and their hardware implementation. Unique complementing scheme, pre-addition of complementing carriers and derivation of sign extensions also reduce hardware implementation as well as allowing the multiplier to handle any combination of input and output formats The principles are also applied to multiplier/accumulators and complex multipliers.

Abstract: A first IGFET and a first bipolar transistor are connected in series between a first power terminaland a first load terminal. A second IGFET and a second bipolar transistor are connected in series between a second load terminal and a second power terminal. the first and second IGFETs are biased to pass the same load current. The first and second bipolar transistors are selectively turned on at the same time to permit current flow via a load which may be connected between the first and second terminals. When the first and second bipolar transistors are turned-off, they prevent conduction (except for leakage) between the load terminals and the first and second power terminals, if and when the voltage at the load terminal goes positive and/or negative. The circuit also includes means for compensating for the base current of the first and second bipolar transistors.

Abstract: First and second outputs of a differential amplifier stage are coupled via first and second selectively enabled transmission gates to first and second inputs of a selectively enabled complementary flip-flop. During a data sensing and acquisition phase, the transmission gates are enabled and the flip-flop is disabled. Although the flip-flop is disabled, two of its cross coupled transistors are coupled via the transmission gates to the differential amplifier stage. This enhances the setting of the flip-flop when it is subsequently enabled and the transmission gates are disabled.

Abstract: A method of forming a high-quality complementary transistor device using bonded wafer technology. The invention includes bonding a handle wafer to a first epitaxial layer and then providing dopants to form the respective N and P buried layers in said first epitaxial layer. A second epitaxial layer is then deposited over the buried layers to provide the device forming regions for the respective transistor devices.

Abstract: An ALU comprising a tree-based carry structure, wherein the maximum fanout from any gate in the carry structure is three. When calculating optimized fanout, it is necessary to consider input capacitance to the following stage. In minimizing propagation delay, it is necessary to consider loading and the number of stages. It has been recognized that optimum fanout of results in optimized propagation through the ALU, thus fanout of three is the closest whole number. A cell has been designed which includes the necessary and sufficient circuitry for building multicell ALU's in a highly optimized structure. The cell provides individually accessible components and dedicated components for optimum layout in the end product.

Abstract: A distributed amplifier having an on chip DC biasing network including a spiral inductor. The spiral inductor has a low resistance for providing a minimal resistance path for the DC biasing, while also having a high inductance for isolating the RF signal from the DC bias sources. Additionally, an inductive lead connected between the spiral inductor and the amplifier has a predetermined inductance such that this inductance is matched with the inherent capacitance of the spiral inductor in order to provide a substantially same impedance as that of the amplifying stages.

Abstract: A method of manufacturing semiconductors formed of bonded wafers. The method includes the use of a heat sink. The heat sink induces a temperature gradient to occur on a single area at the interface of the wafers with the gradient moving rapidly across the remaining surface. As a result of the temperature front, the voids or uncontacted areas between the wafers which result in a typical bonding process are substantially reduced, thereby providing a stronger and more effective bond.

Abstract: A method of forming a high quality dielectrically isolated silicon on insulator semiconductor device using a double wafer bonding process. As a result of the double wafer bonding process, the invention significantly reduces the device limitations presently known with dielectric isolation and silicon on insulator structures. The present invention specifically eliminates the need for grinding or polishing the final surface which the devices will be implemented in, thereby eliminating the adverse effects which these mechanical processes impute onto these surfaces. Additionally, the present invention eliminates the need for a thick polycrystalline deposition for the production of the dielectric isolation, thereby eliminating the adverse effects of single crystal bulk defects and the loss of tolerance control due to warpage which would otherwise occur in a dielectric isolated process.

Abstract: A process for the formation of a compact vertical contact having reduced lateral space requirements yet compatible with highly planarized semiconductor manufacturing processes. The contact is made from a foundation region having a top surface to an overlying layer separated from the foundation region by a dielectric. The overlying layer can be contacted on its edge rather than on its top surface in order to reduce the lateral expanse of the contact.

Abstract: A monolithic semiconductor having an on-chip DC biasing including a plurality of series connected spiral inductors connected between the respective biasing and the semiconductor circuit. The spiral inductors provide a low resistive path for the DC biasing while also having a high inductance for isolating the RF signal from the bias sources, thereby improving the low frequency response. The capacitance associated with the individual spirals, however, is significantly less than the capacitance associated with a single spiral inductor having an equivalent inductance of the small series connected spirals; thus the higher frequency response is not degraded while the low frequency response has been improved.

Abstract: The present invention provides an improved lateral drift region for both bipolar and MOS devices where improved breakdown voltage and low ON resistance are desired. A top gate of the same conductivity type as the device region with which it is associated is provided along the surface of the substrate and overlying the lateral drift region. In an MOS device, the extremity of the lateral drift region curves up to the substrate surface beyond the extremity of the top gate to thereby provide contact between the JFET channel and the MOS channel.

Abstract: A pallet for conveying a plurality of ceramic leadless chip carriers (LCC) through an automated wave soldering machine. The pallet includes recesses formed to receive and contain the LDD's with the lid of the LCC facing into the recess. This results in protecting the lids from the molten solder. Additionally, the recesses are formed in a diamond orientation with a solderable pin placed at the trailing apex of each recess. Both the pin and the diamond orientation prevents solder build up on the trailing conductive pads, resulting in enhancing the coplanarity of the solder on the pads.

Abstract: The front end of an operational amplifier having an improved slew rate and high gain current output capabilities. The amplifier includes a slew enhancement or large signal stage connected in parallel to a normal front end or small signal stage. The small signal stage supplies a transconductance output which is approximately linearly related to the input until its slew rate limit. The slew enhancement stage is designed to provide slew current when the small signal stage reaches a selected threshold such as its slew rate limit, thereby providing an increased output current response to an increasing differential input voltage beyond the slew rate of the small signal stage. The large signal stage can be optimized to provide a greater input linear dynamic range, faster slew rate and improved efficiency.