Abstract: A method of forming a pre-molded lead frame having increased stand-offs includes the steps of attaching a first tape to a first side of the lead frame and a second tape to a second side of the lead frame. The taped lead frame is placed in a mold and a first flow of mold compound is initiated. The first flow of the mold compound fills a space between the first tape and an upper mold chase of the mold. A second flow of the mold compound then is initiated. The second flow of the mold compound fills the spaces between a die pad and leads of the lead frame. The first and second tapes then are removed from the lead frame. Improved stand-offs are provided because the first tape was depressed by the first flow of the mold compound.

Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface (112) attached to the base carrier top side (108), and an opposing, top surface (114). The top surface (114) has a peripheral area including a plurality of first bonding pads and a central area (120). A bead (124) is formed on the top surface (114) of the bottom die (104) between the peripheral area and the central area (120). A top integrated circuit die (106) having a bottom surface is positioned over the bottom die (104) and the bottom surface of the top die (106) is attached to the top surface (114) of the bottom die (104) via the bead (124). The bead (124) maintains a predetermined spacing between the bottom die (104) and the top die (106) so that wirebonds of first wires (122) connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).

Abstract: A method of packaging an integrated circuit die (12) includes the steps of providing a foil sheet (30) and forming a layer of solder (32) on a first side of the foil sheet. A first side of the integrated circuit die is attached to the solder on the foil sheet. The first side of the die has a layer of metal (34) on it and a second, opposing side of the die includes bonding pads (14). The bonding pads are electrically connected to the solder on the foil sheet with wires (16). The die, the electrical connections, and the first side of the foil sheet are encapsulated with a mold compound (20). The foil sheet is separated from the die and the wires, which forms a packaged integrated circuit (10).

Abstract: A driver circuit that allows high-speed switching when the reference current (I) is small. The driver circuit includes a drive current generation circuit (220) for supplying to a first node (232) a drive current based on a binary data signal (DATA); a current mirror circuit (240) for conducting through a second node (234) a current (mI) having a magnitude of the current flowing through the first node (232), multiplied by a predetermined current mirror ratio (m); and a pre-bias circuit (260) for supplying a first pre-bias current (Ib1) to the first node (232) and supplying a second pre-bias current (Ib2) having a magnitude of the first pre-bias current (Ib1), multiplied by said current mirror ratio (m), to the second node (234).

Abstract: A low drop out voltage regulator (10) that receives an input voltage and generates a substantially constant output voltage includes a gain stage (12), a buffer stage (14), an output driver transistor (16), and first and second load current sense circuits (18, 20). The first load current sense circuit is connected between the output driver transistor and the buffer stage and adaptively increases a bias current of the buffer stage as a function of the load current. The second load current sense circuit is connected between the output driver transistor and the gain stage and adaptively decreases a bias current of the gain stage as the load current increases.

Abstract: A leadframe (20) for a semiconductor device includes a first leadframe portion (12) having a perimeter that defines a cavity (16) and a plurality of leads (14) extending inwardly from the perimeter and a first thickness. A second leadframe portion (18) is attached to the first leadframe portion (16). The second leadframe portion (18) has a die paddle (20) received within the cavity (16) of the first leadframe portion (12). The second leadframe portion (18) has a second thickness that is greater than a thickness of the first leadframe portion (12). Such a dual gauge leadframe is suitable especially for high power devices in which the die paddle acts as a heat sink.

Abstract: An image sensor device includes a first, QFN type leadframe to which a sensor IC is electrically connected. A second leadframe is provided for holding a lens. A third leadframe is positioned between the first and second leadframes to appropriately space the IC from the lens. Multiple sensor devices are assembled at the same time by the use of leadframe panels.

Abstract: An image sensor device is made using an ultra-thin substrate so that the overall device height is less than 1.0 mm. The image sensor includes a flexible circuit substrate having first and second opposing sides, the first side having a central area and an outer, bonding pad area including bonding pads. A sensor integrated circuit (IC) is attached to the central area of the first side of the circuit substrate. The IC has an active area and a peripheral bonding pad area including bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the circuit substrate bonding pads to electrically connect the IC and the circuit substrate. A wall having a first end with a step and a second end has its second end attached to an outer portion beyond the outer bonding pad area of the first side of the flexible circuit substrate. The wall at least partially surrounds the sensor integrated circuit.

Abstract: A glitch removal circuit that removes both positive and negative glitches from an input signal includes a delay circuit, a glitch blocking circuit, and a latch circuit. The delay circuit receives the input signal and introduces a delay into it. The glitch blocking circuit is coupled to the delay circuit, and includes two NMOS transistors and two PMOS transistors. The glitch blocking circuit receives the input signal and the delayed input signal and blocks the input signal if there is a glitch in it. The latch circuit is coupled to the output of the glitch blocking circuit. The latch circuit inverts the output of the glitch blocking circuit and stores the output on a continuous basis. The latch circuit provides glitch free signal as the output.

Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface (112) attached to the base carrier top side (108), and an opposing, top surface (114). The top surface (114) has a peripheral area including a plurality of first bonding pads and a central area (120). A bead (124) is formed on the top surface (114) of the bottom die (104) between the peripheral area and the central area (120). A top integrated circuit die (106) having a bottom surface is positioned over the bottom die (104) and the bottom surface of the top die (106) is attached to the top surface (114) of the bottom die (104) via the bead (124). The bead (124) maintains a predetermined spacing between the bottom die (104) and the top die (106) so that wirebonds of first wires (122) connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).

Abstract: A semiconductor device 30 includes a base carrier 32, an adhesive material layer 36 and an integrated circuit die 34. The base carrier 32 has a top side and a bottom side, the top side having a central area for receiving the die 34 and a peripheral area surrounding the central area. The adhesive material layer 36 is disposed on the top side of the base carrier in an “X” shaped pattern. The “X” shaped pattern includes two bisecting lines. The two bisecting lines extend well beyond the central area and into the peripheral area of the base carrier top surface. The die 34 is attached to the base carrier 32 with the adhesive material layer 36 at the central area. Even after attachment of the die 34, the adhesive material 36 extends well beyond the die 34 and the central area into the peripheral area.

Abstract: A low bit rate phase excited linear prediction type speech encoder filters a speech signal to limit its bandwidth and then fragments the filtered speech signal into speech segments. The speech segments are decomposed into a spectral envelope and an LP residual signal. The spectral envelope is represented by LP filter coefficients. The LP filter coefficients are converted into line spectral frequencies (LSF). Each speech segment is also classified as one of a voiced segment and an unvoiced segment based on a pitch of the segment. Parameters are extracted from the LP residual signal, where for an unvoiced segment the extracted parameters include pitch and gain and for a voiced segment the extracted parameters include pitch, gain and excitation level. The extracted parameters are then quantized.

Abstract: A semiconductor device (10) includes a first leadframe (18) having a perimeter (20) that defines a cavity (22) and leads (14) extending inwardly from the perimeter, and a second leadframe (32) having top and bottom surfaces and a die paddle surrounding a die receiving area (36). An integrated circuit (12) is placed within the die receiving area of the second leadframe. The IC has bonding pads (44) located on a peripheral portion of its top surface. The second leadframe and the IC are in facing relation with the first leadframe such that the leads of the first leadframe are electrically connected to respective ones of the bonding pads. A mold compound (50) is injected between the first and second leadframes and covers the second leadframe top surface and a central area of the first surface of the IC. At least the bottom surfaces of the leads are exposed.

Abstract: A leadframe (20) for a semiconductor device includes a paddle ring (22) having an inner perimeter (24), an outer perimeter (26), and a cavity (28) located within the inner perimeter (24) for receiving an integrated circuit die (30). A first row of terminals (32) surrounds the outer perimeter (26) and a second row of terminals (34) surrounds the first row of terminals (32). Each of the terminals of the first row of terminals (32) is individually connected to the paddle ring (22) and each of the terminals of the second row of terminals (34) is connected to one side of a connection bar (78, 79), which is connected to one of the terminals of the first row (32) or to the paddle ring (22).

Abstract: A method for selecting cells in response to input codes of a digital-to-analog converter distributes noise based on cyclicality of selection patterns to reduce its value, without being dependent upon the input codes. A 6-bit current output type digital-to-analog converter has 63 current source cells C01 through C63. A prime number of, or 61, current source cells are used as cyclically selected cells. That is, 61 current source cells C02-C62, ranging from the second left-most current source cell C02 to the second right-most current source cell C62, are used as cyclically selected cells. The remaining left-most current source cell C01 and right-most current source cell C63 are used as non-cyclically selected cells. The cyclically selected cells, including the 61 current source cells, are selected in response to input codes using a Data Weighted Average (DWA) technique.

Abstract: A switched capacitor current reference circuit generates an almost constant reference current across the parameters of process, voltage and temperature. A reference voltage is generated within the circuit, which eliminates the need for an external reference voltage. The reference current is generated by applying the reference voltage across a resistor emulated with a pair of switched capacitor circuits.