Abstract: A compact coupling arrangement between a light source and a plurality of light distribution harnesses includes a plurality of reflector members arranged around the light source with respective focal points of the reflector members positioned substantially coincident with the light source, so as to receive light from the source and reflect the light away from the source. Further included is a plurality of light coupling members, each having an inlet and an outlet surface for receiving light originating from the light source and transmitting light, respectively. A plurality of light distribution harnesses is provided for respectively receiving light from the light coupling members. The light coupling members each comprise a lens having a negative curvature in at least one direction generally transverse to a main light transmission axis therethrough, for receiving light at a first angular distribution and transmitting light at a reduced angular distribution.

Abstract: The invention relates to an acoustic piano having a fretbase on which at least one fret node is supported by a fret and an adjacent node spaced from the fret node. Selected piano strings press downwardly upon the nodes and define between the nodes a duplex scale portion of the piano strings. A plate is located beneath the fretbase and is pressed downwardly by the fretbase due to pressure of the strings. The invention provides a method of moving the fretbase portion relative to the plate in a direction parallel to the piano strings. The method includes the steps of providing a force-applying tool including a mandrel portion, and a force-transmitting head having a force-transmitting surface and a surface for sliding on the plate. The tool is oriented so that a main axis of the mandrel portion angles downwardly towards a plane of the piano strings, with the force-transmitting surface abutting a force-receiving surface of the fretbase, and with the sliding surface abutting the plate.

Abstract: A device for holding hair in a bundle comprises a body member configured in a generally spiral manner from proximate a main axis of the device to an opening for receiving hair. Portions of the body member that are radially adjacent to each other with respect to the main axis present confronting surfaces for applying pressure to hair and define a generally spirally shaped hair-receiving volume. A sufficient extent of the body member preferably comprises resilient material for allowing an ordinary user to increase the hair-receiving volume, during insertion of the device into a bundle of hair, more than about 50 percent in an outermost 180.degree. spiral region bounded by the hair-receiving opening. When the device is unflexed, the hair-receiving volume preferably decreases in radial dimension with respect to the main axis more than about 15 percent from a radially outer, to a radially inner, portion of one spiral turn of the hair-receiving volume other than innermost and outermost 45.degree.

Abstract: Disclosed is a method of connecting the terminals of at least one heat-sinked, plastic-encapsulated power transistor to circuits of a printed-circuit board. In the method, a main flat surface of the plastic-encapsulated power transistor is adhered to a first side of a heat sink. The transistor has a plurality of terminals projecting from one end of a transistor body in an orientation generally parallel to the main flat surface of the transistor. On a printed-circuit board, a mechanical coupling device is mounted that has respective conductors with respective, terminal-receiving apertures, for receiving the terminals of the transistor. The conductors are connected to respective circuits of the printed-circuit board. The printed-circuit board is adapted to be located on the mentioned one side of the heat sink in an assembled position. The heat sink, with the transistor mounted thereon, is positioned such that the terminals are respectively inserted into respective apertures in the mechanical coupling device.

Abstract: A silicon circuit board incorporates multiple levels of patterned conductors. First level upper and lower patterned conductors are situated on an insulation-coated, monocrystalline silicon substrate. Upper and lower, high resistivity, polycrystalline silicon layers, in turn, are situated on the first level upper and lower patterned conductors, respectively. Second level upper and lower patterned conductors are situated over the upper and lower polycrystalline silicon layers. Further levels of patterned conductors in the circuit board may be provided by iteratively forming on the board polycrystalline silicon layers and patterned conductors. Conducting feedthroughs in the circuit board provide electrical communication between various patterened conductors.

Abstract: An electrical circuit includes a JFET serially connected to an IGFET, the gate of the IGFET constituting the gate for the circuit. Biasing structure, such as a resistor, is connected between the circuit gate and the gate of the JFET for forward-biasing the P-N junction of the JFET extant between its gate and channel regions. When this P-N junction is biased by more than about 0.6 volts for a silicon JFET, the JFET gate region injects current carriers into the JFET channel region, whereby bipolar conduction occurs in the JFET channel region and low on-resistance for the circuit is achieved. In a preferred circuit the biasing structure comprises an IGFET, which advantageously results in the circuit gate having a high input impedance.

Abstract: A method for preparing high density yttria-gadolinia ceramic scintillators by cold-pressing multicomponent powder to form powder compacts and then sintering the compacts to form transparent-to-translucent ceramic scintillator bodies. The powder compacts are formed by either die pressing or die pressing followed by isostatic pressing to further increase green density. The powder compacts are sintered in vacuum or a reducing atmosphere at a temperatue of between 1800.degree. C. and 2100.degree. C. The preferred heating sequence includes a holding period at a temperature lower than the final sintering temperature. The finished scintillator includes Y.sub.2 O.sub.3, Gd.sub.2 O.sub.3, and one or more of Eu.sub.2 O.sub.3, Nd.sub.2 O.sub.3, Yb.sub.2 O.sub.3, Dy.sub.2 O.sub.3, Pr.sub.2 O.sub.3, and Tb.sub.2 O.sub.3 rare earth activator oxides. At least one of the oxides of elements Zr, Th, and Ta is included as a transparency promoting densifying agent.

Abstract: Double diffused power MOSFET's and methods of manufacture. The source, base and drain regions of a double diffused power MOSFET correspond respectively to the emitter, base and collector of a parasitic bipolar transistor. Double diffused power MOSFET's perform better when provided with an ohmic short between the source and base regions to prevent turn-on of the parasitic bipolar transistor. In one form of ohmic short between the base and source regions, the source terminal comprises a metallic electrode, preferably aluminum, deposited over the source region, and the ohmic short comprises at least one microalloy spike extending from the source terminal metallic electrode through the source region and partly into the base region. Such microalloy spikes are formed by heating the semiconductor substrate after the metallic electrode has been deposited under appropriate conditions. In another form, a V-groove is formed by preferential etching in the source and base regions.

Abstract: A semiconductor device incorporates a JFET serially connected to a bipolar transistor to achieve normally-off operation. An impedance element is connected between the base of the bipolar transistor and the gate of the JFET, which serves as a single control electrode for the entire device. When a current is supplied to the control electrode, the bipolar transistor and JFET are both switched to the on state. In the JFET, the p-N junction between the gate region and the channel region is sufficiently forward-biased so as to inject current carriers into its channel region and markedly reduce the device on-resistance. An electrical circuit analogue of the device achieves the advantage of low on-resistance and normally-off operation.

Abstract: An electrical assembly includes a conductor pattern, a non-metallic substrate, and a eutectic alloy situated between and bonding together the conductor pattern and the substrate. The conductor pattern includes an area with a surface facing the non-metallic substrate but spaced from the substrate. A method of fabricating such assembly includes, prior to bonding, the step of partially penetrating through the side of the metallic sheet to be bonded to the substrate in selected areas of the sheet. The remaining metal of the sheet in each selected area does not bond to the substrate during a eutectic bonding procedure.

Abstract: An X-ray imaging system includes a phosphor that exhibits a fast-acting photoluminescent response both in luminescing upon X-ray stimulation and ceasing to luminesce upon cessation of X-ray stimulation. The phosphor has the general formula A.sub.2 MX.sub.6 wherein A is selected from Cs, Rb, Na and K; M is selected from Ti, Zr, Hf, Te and Sn; and X is selected from Cl and Br. In one form the phosphor has a purity with respect to naturally-occurring impurities of at least about 98.0 percent (by weight) and is sufficiently deficient of luminescent activators effective only at very low temperatures that the phosphor luminesces at higher temperatures.

Abstract: A P-N diode includes a P.sup.- substrate with a thin N.sup.- epitaxial layer thereon. A P.sup.+ isolation region surrounds the periphery of the N.sup.- epitaxial layer and is integrally connected to the P.sup.- substrate. An N.sup.+ cathode region extends into the N.sup.- epitaxial layer from the upper surface of such layer. A P.sup.+ anode region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region. A further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region, and, in turn, is surrounded by the P.sup.+ anode region. The further P.sup.+ region is biased at the same potential as the P.sup.- substrate. An N.sup.+ buried layer is situated between the P.sup.- substrate and the N.sup.- epitaxial layer, beneath the P.sup.+ anode region, and surrounds the N.sup. + cathode region. An N.sup.+ sinker region extends into the N.sup.

Abstract: A highly multiplexed liquid crystal display employs nonlinear varistor elements exhibiting a particularly low capacitance value to effectively drive individual liquid crystal cells. Low varistor capacitance is achieved through controlled addition of Sb.sub.2 O.sub.3 during varistor manufacture.

Abstract: Process for manufacturing insulated-gate semiconductor devices such as MOSFETs being with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. A two-stage polysilicon etch procedure is disclosed. The initial etch produces relatively narrow channels with substantially vertical sidewalls. Unetched portions of the polysilicon layer are used as masks during a first P type diffusion to form a shorting extension of the device base region and during the forming of a silicon nitride mask layer by a highly directional process, such as ion implantation, which avoids the formation of any nitride layer on the channel sidewalls. In a subsequent lateral etch step, previously unetched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures.

Abstract: Methods for fabricating vertical channel buried grid field controlled devices with improved performance characteristics include methods which avoid the problems caused by autodoping effects. In one form of the invention, one surface of a semiconductor substrate is preferentially etched to form substantially vertically-walled grooves, and the grooves are selectively refilled employing vapor phase epitaxial growth to form a grid structure. A semiconductor layer is then epitaxially grown over the substrate surface and grid so as to bury the grid. In another form of the invention, grooves are preferentially etched in semiconductor substrate to achieve steep vertical walls. Thereafter, the grooves are either partially refilled by means of epitaxial growth or, preferably, completely refilled and then again preferentially etched to remove a predetermined fraction of the refilling. A second epitaxial refill is done to fill the remainder of the grooves.

Abstract: A surge condition in a stalled gas turbine engine is promoted by modulating a time-varying component of an operating parameter of the gas turbine engine, such as the fuel flow to the combustor plenum of the engine, substantially in phase with a time-varying component of the pressure in the combustor plenum, thereby allowing normal operation of the engine to resume during the surge condition by eliminating the stall-inducing agent.

Abstract: Solderable, largely base metal electrodes for metal oxide varistors are fabricated by screen printing an electrically conductive, air-fireable base metal composition on a varistor material substrate. A distributed fine noble metal array is screen printed over the screened base metal and the varistor heated in air at a temperature of between approximately 500.degree. C. and 800.degree. C. The varistor leads are easily solderable to the noble metal array.

Abstract: A thermistor suitable for use in a temperature range with a maximum temperature exceeding 400.degree. C. comprises bulk thermistor material with a pair of electrical leads attached to the thermistor material by respective quantities of conductive paste each having a curing temperature substantially in excess of the aforementioned maximum temperature.