Abstract: Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS topography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the water and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.

Abstract: A microprocessor for facilitating use of FORTH computer language includes a top register for storing a first parameter and an Arithmetic logic unit (ALU) connected to the top register for processing the first parameter with other parameters and for storing the results in the top register. An index register stores a second parameter and addresses main memory and pops and pushes the second parameter with respect to a return Last in/first out (LIFO) stack. A next parameter register stores a third parameter and pops andpushes the third parameter with respect to a next parameter LIFO stack. Anh addressing multiplexer is coupled to the index register and the next parameter register. A first swap connection to the top and index registers enables single cycle exchange of the first and second parameters between these two registers. A second swap connection between these registers permits a single cycle exchange of the first parameter and the third parameter between the top and next parameter registers.

Abstract: The gain of a parasitic lateral bipolar device in an MOS SOI structure is reduced to increase the differential between the snap-back sustaining voltage and the maximum recommended power supply voltage. Prior to insulated gate structure definition, very lightly doped source and drain regions are implanted to the underlying insulator layer. The source and drain regions have a doping concentration that is within an order of magnitude of the doping concentration of the well portion of the semiconductor layer. After the very lightly doped regions have been implanted, the implant mask is stripped and an insulated gate structure is formed atop the channel surface portion of the well layer between the source and drain regions. Using the insulated gate structure as a mask, off-axis, high angle implants of the same conductivity type as the source and drain regions are carried out to a first depth that only partially penetrates the depth of the deep source and drain implants.

Abstract: A miniaturized cylindrical `channeline` delay line comprises a plurality of concentrically stacked cylindrical elements, surfaces of which are configured to form helically contoured `channeline` transmission line. The nested stack includes a first, generally cylindrical conductive spool body element, for example a lightweight and electrically conductive cylinder or spool, having a longitudinal axis and an outer, generally cylindrical surface in which a helical groove is formed. Concentrically surrounding this interior spool are one or more additional, generally cylindrical hollow electrically conductive hollow cylinders of successively increasing diameters. These additional electrically conductive hollow cylinders are sized, so that respective ones of the cylinders may be concentrically stacked about the longitudinal axis of the interior spool. Like the interior spool, each surrounding cylinder has a helical groove formed in its outer cylindrical surface.

Abstract: The thickness of a DI island structure is reduced and the performance of bipolar and JFET structures enhanced by shaping the bottom of the DI island during anisotropic etching to define isolated islands, so that the resulting structure contains one or more projections whose separation from the topside diffusion predefines operational characteristics of the device. If the projection is directly beneath the bottom of a gate diffusion, pinch-off voltage of a JFET device is reduced without substantially affecting channel resistance. When the projection is positioned so that its inclined surface extends alongside the curvilinear PN junction formed between the gate diffusion and the island, channel thickness and sensitivity of channel thickness to viriations in island thickness are reduced.

Abstract: A rectilinear motion proportional solenoid assembly includes a cylindrical housing containing an electromagnetic coil having a longitudinal coaxial bore. The housing contains magnetic material for providing a flux path for the magnetic field produced by the coil. A generally cylindrical magnetic pole piece element is inserted into the bore and a movable armature assembly of magnetic material is supported within the bore for movement along the longitudinal axis of the coil by a pair of thin, flexible suspension springs. One of the springs is located within the bore adjacent to one end of the magnetic pole piece whereat an axial gap between the pole piece and the armature is formed. A second spring is located within the housing within the vicinity of a radial air gap between the armature and the housing.

Abstract: A high speed voltage switching circuit comprises symmetrically arranged voltage relay transistor circuits coupled between voltage input terminals and a switched voltage output terminal. A first voltage relay transistor circuit relays a first voltage at the first input terminal to the output terminal in response to the controlled application of current directly to the output terminal from a first switched current source. A second voltage relay transistor circuit relays a second voltage at the second input terminal directly to the output terminal in response to the removal of current from the output terminal by way of a second switched current source. Each voltage relay transistor circuit preferably comprises pairs of bipolar transistors having their base-emitter junctions coupled in series between the first voltage input terminal and the output terminal.

Abstract: A bridge-configured precision voltage reference circuit includes a first voltage supply terminal, a second voltage supply terminal, first and second bridge nodes, and a bridge resistor connected between the first and second bridge nodes. A Zener diode is coupled between the first bridge node and the first voltage supply terminal, and a voltage divider circuit is coupled between the first voltage supply terminal and the second bridge node. An output voltage terminal is coupled to the voltage divider circuit, so that a precision output voltage is derived as a fraction of the voltage differential between the second bridge node and the potential of the first voltage supply terminal. A fixed magnitude current source is coupled between the first bridge node and the second voltage supply terminal, and an adjustable current source is coupled between the second voltage supply terminal and the second bridge node.

Abstract: Character segmentation apparatus for an optical character recognition system for segmenting individual character images in an image of a document having many characters prior to performing character identification, including a movable kernel for capturing a sub-image framed within a window having an area corresponding to an area occupied by an individual character, the window being movable in the document image in pixel-by-pixel steps to capture a sub-image for each step of the window, an associative memory for responding to the captured sub-image by producing a corresponding one of a set of images of known characters with which the associative memory has been trained, and a sensor responsive to the behavior of the associative memory for determining whether the sub-image is the image of an individual character or a non-character.

Abstract: Interpolation processing of digital map imagery data is carried out by prefetching full and half resolution data stored in half-resolution addresses of scene memory into a cache and accessing the cache as virtual addresses associated with the interlaced scan of the display are generated. Both full and half-resolution data is controllably weighted and summed bi-linearly to obtain interpolated data values for spatial locations corresponding to the virtual addresses. For a respective half-resolution storage location, stored imagery data includes both half-resolution data, (such as that representative of color characteristics, elevation, cultural features, linear and area features) of its associated half-resolution spatial location in a terrain map and a plurality of full-resolution data for a plurality of full-resolution spatial locations of the terrain map that are located in a adjacent neighborhood surrounding the half-resolution spatial location.

Abstract: A preamorphized silicon layer formed atop a sapphire substrate is selectively recrystallized such that the original degraded quality of the crystallinity of an N-well region where a P-channel device is to be formed is enhanced, so that leakage in the P-channel device is reduced, while the high UVR number of a P-well region where an N-channel device resides remains unaffected. The process according to the present invention involves implanting a recrystallization-inducing element, such as silicon, into only that portion of the preamorphized silicon layer where an N-conductivity well region for a P-channel device is to be formed. An N-conductivity type impurity is introduced into the silicon-implanted portion of the preamorphized silicon layer, to form the N-conductivity well region.

Abstract: A laser driver mechanism for image reproduction maintains linear operation over a wide frequency an dynamic range of amplitude-modulated input signals by means of a first feedback loop and a second feedback loop. The second feedback loop contains a first amplifier coupled to receive the input signals and an output coupled to a second amplifier that drives an injection laser diode. A photodetector is coupled downstream of and external to a sealed unit in which the injection laser diode emitter, an associated photodetector of the first feedback loop and beam extraction optics are housed. The photodetector of the second loop has an output coupled to the second amplifier, so that the second feedback loop serves to compensate for non-linearities in the laser driver including those of the first feedback loop.

Abstract: An SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at an end portion of the extended body region, so as to provide a channel stop region that is effective to functionally interrupt a current leakage path or `parasitic` N-channel that may be induced along sidewall surface of the P-type material of the body/channel region. In addition, in order to inhibit radiation-induced leakage along a backside interface of the extended body region abutting an underlying dielectric substrate, a portion of the extended body region between the channel stop region and the body/channel region has an impurity concentration profile that is increased at the interface of the extended body region with the underlying dielectric substrate.

Abstract: A tape automated bonding feeder apparatus employs a vertical carrier extraction unit to successively supply electronic circuit components to an output station from which a component is seized for placement and attachment to a circuit board. The feeder apparatus, which may be mounted on a rollable cart, includes a generally rectilinear housing on a top plate of which one or more magazines are mounted. A magazine contains a stack of circuit component carriers. The bottom of the magazine has a carrier extraction unit which controllably allows an individual component carrier at the bottom of the stack to drop away onto an underlying carrier shuttle. The carrier shuttle is supported for movement between the magazine and a lead forming unit. The lead forming unit detaches a component from the carrier and forms the leads of the excised component for mounting the component to a circuit board.

Abstract: The trench pattern of a dielectrically isolated island architecture is filled with doped polysilicon and used as an interconnect structure for circuit devices that are supported within the islands, thereby decreasing the amount of topside interconnect and reducing the potential for parasitics beneath tracks of surface metal. The trench pattern may serve as a voltage distribution network or provide crossunders beneath surface tracks. In addition, at least one of the islands may contain one or more auxiliary poly-filled trench regions to perform the crossunder function. Such an auxiliary trench region may be also provided in an island that contains a circuit device. Manufacture of the conductor-filled trench structure may be facilitated by depositing polysilicon over a dielectrically coated trench grid structure and then planarizing the polysilicon to the surface of the oxide dielectric. The exposed polysilicon is doped and then oxidized to seal the dopant, which forms a thin oxide layer on the poly.

Abstract: A process for removing unwanted contaminant metallic oxide from the surface of a nickel branding layer of an electronic circuit package, in order to enhance the affinity of a layer of phenolic branding ink to the surface of the metallic branding layer involves treating the surface of the metallic branding layer with a hydrogen-containing, chemical reducing gas phase ambient, so that oxygen within the surface oxide chemically combines with the hydrogen component within the ambient, so as to form readily removable water. The surface of the metallic branding layer is thereby substantially free of surface oxide, providing a greater surface area of metallic-ink bonding sites. As a consequently, a subsequently deposited layer of branding ink strongly adheres to the surface of the nickel and is not readily removed during further cleaning of the circuit package.

Abstract: A transformer unit mountable above the cutting deck of a mid-size, walk behind rotary mower, effectively converts the mower into a riding mower. The transformer unit is configured so as to allow an operator to be seated above the cutting deck, while still being able to comfortably control the mower by means of the original operator control handle, which is relocated by the transformer unit to the front end of the mower. The transformer unit comprises a support frame which is affixed to a cutting deck support structure. The support frame includes a vertically tiltable floor unit that extends over the top of cutting deck. An auxiliary operator control handle attachment fixture is mounted to the forward end of the support frame adjacent to the front end of the mower and is configured to engage and support the operator control handle, such that the operator control handle extends above the cutting deck adjacent to a position where the operator is to be situated.

Abstract: A surge suppressor for a high frequency transmission line contains a microstrip architecture comprising a dielectric sheet on a first side of which a signal conductor stripe layer is formed and on a second side of which a ground plane conductor layer is formed. The strip layer is disposed along a generally central linear region of the first surface, so as to facilitate direct connection to the center conductor of a pair of end connectors, such as type F coaxial connectors. The ground plane conductor layer is attached to the shield layer of the coaxial connectors. A gas discharge tube is coupled between a first location of the stripe layer and the ground plane layer. The discharge device may be mounted on the first side of the microstrip structure and is connected to the ground plane layer on the opposite surface by way of a plated through hole.

Abstract: A high isolation broadband switching circuit includes a plurality of switching elements coupled in series alternatingly with transmission line segments. Each switching element has a low or very high impedance between first and second points responsive to first and second values of a control voltage, respectively. In a first embodiment, the switching element includes a PIN diode having a cathode coupled to a first transmission line and an anode coupled to a second transmission line. In a second embodiment, the switching element includes a field effect transistor (FET) having a drain coupled to a first transmission line and a source coupled to a second transmission line. A first resistor is coupled between the drain and the source for DC continuity between the drain and the source, and a second resistor coupled between a gate of the FET and ground for DC continuity. A bias voltage source is coupled through a resistor to one of a source and a drain of one of the FETs.

Abstract: Creation of structural defects in a trench-isolated island structure is obviated by protecting the bottom of the trench pattern during etching of the hard mask surface oxide. A layer of photoresist is non-selectively deposited on the hard mask oxide layer and in the trench pattern, so that the photoresist buffer layer fills the trench pattern and is formed atop the hard mask oxide layer. The deposited photoresist is controllably flood-irradiated, so as to expose the irradiated photoresist down to a depth in the trench pattern that is at or somewhat deeper than the surface of the hard mask insulating material. The exposed photoresist is then developed, so as to remove the irradiated depth portion of the photoresist lying atop the hard mask oxide layer and partially extending into the trench, thus exposing the hard mask oxide layer, but leaving a sufficient quantity of unexposed photoresist in the trench pattern that provides a surface barrier for the underlying oxide.