Abstract: A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation.

Abstract: A data storage device having the capability of preventing unauthorized access to data stored therein, including a memory, e.g., a flash EEPROM, having a first portion for storing a plurality of internal passwords and a second portion for storing address data, e.g., encoded password addresses and status identification data, indicating the location of the internal passwords in the first portion, a control circuit responsive to an access request signal from an external device, e.g.

Abstract: A semiconductor memory device, e.g., a DRAM, which includes a P-type semiconductor substrate, a memory array each memory cell of which includes at least one N-channel MOS transistor, a CMOS peripheral circuit at least partially surrounding the memory array, the peripheral circuit including at least one P-channel MOS transistor formed in an N-type well region formed in the substrate, and at least one N-channel MOS transistor formed in the substrate outside of the N-type well region, and, a P-type minority carrier absorption semiconductor region formed in the substrate between the N-type well region and the memory array. The minority carrier absorption semiconductor region is preferably connected to a source of negative voltage, e.g., the substrate bias voltage, and a separate N-type region formed in the N-type well region is preferably connected to a source of positive voltage, e.g., the power supply voltage, Vdd, of the memory device.