Abstract: A voice coil motor driving circuit 10 with retracting function used in a disk drive unit for driving a read/write head by means of a voice coil motor VCM, comprising a voltage up-converter 12; a voice coil motor control circuit 16 for driving the voice coil motor during normal operation; a retract power source Vrr for supplying a retract current to the voice coil motor during head retract action; a retract control circuit 24 for allowing the retract current from the retract power source to the voice coil motor in response to a retract signal. The driving circuit also includes a capacitor C for providing an uninterrupted supply of voltage to the retract control circuit 24 during head retract action.

Abstract: Two storage capacitors connected in parallel with a constant current source in a charging mode and connected in series in a second mode to increase output voltage. A comparator senses the amplitude of the output voltage and controls the current supplied to the capacitors in the charging mode to increase or decrease the output voltage to coincide with a predetermined amplitude.

Abstract: This invention relates to a bias current control circuit which drives a power MOS transistor. Since the power MOS transistor has a large capacitance which is formed between a gate and a channel, it is needed to provide a circuit which is able to sufficiently supply a drive current to the gate. Such a circuit increases a consumption current because the circuit has to always flow the current to drive the gate. This invention provides a circuit which cut the consumption current in the circuit when the transistor is not driven, and increases a consumption current in the circuit in order to keep a gate current when the transistor is driven.

Abstract: A method of providing IC layouts for a family of LCD drivers including the steps of separating the driver into a front end section and a driver section, determining the number of backplanes and frontplanes and the number and size of voltage levels required, generating a resistor ladder voltage generator with the required number and size of levels, generating individual cell layouts for each of the major components, and building pitch matched layouts of the components from the cells.

Abstract: A microprocessor including a CPU, an instruction memory (ROM) with a sequencer in the CPU that sends out a fetch signal for an instruction, and an address decoder that decodes the fetch signal and sends a signal to the ROM allowing the fetch signal to fetch an instruction if the address is correct.

Abstract: A bonding pad is described having a reduced surface area while maintaining adequate wire bonding surface. The bonding pad comprises: a test pad for contacting with a test probe; a plurality of radially extending conductive fingers; and an alignment key generally in the form of a circle disposed about a portion of the fingers.

Abstract: Heat removal is accomplished by utilizing a first metal conductive pad to conduct the heat from an electrical component. The first pad is juxtaposed and thereby thermally coupled by convection to one or more ground pads having plated through holes to a ground plane and heat sink.

Abstract: A method and apparatus for electroplating metallized bumps of substantially uniform height on predetermined terminal areas of a substrate. Cup plating apparatus includes elements for adjusting parameters affecting the geometry of the substrate relative to the plating cup, as well as flow rate of the electroplating solution against the substrate surface. By achieving non-laminar flow of the electroplating solution near the substrate edges, the plating characteristics of the electroplating solution are altered in this region, substantialy offsetting "edge effect", so that the resulting plated bump height is substantially uniform across the substrate.

Abstract: There is described a low voltage sense amplifier for an EPROM memory transistor which has a low voltage inverter coupled to the memory transistor. The inverter receives a selectable low reference voltage as its power supply and the same reference voltage is fed as a precharge voltage, prior to reading an EPROM bit, to the input of the inverter.

Abstract: A multifunction ground plane for an electrical device such as an integrated circuit is provided by a plurality of conductors each having one end thereof adapted to be coupled to the electrical device with a ground plane adjacent and electrically isolated from said plurality of conductors. The ground plane includes a plurality of electrically isolated portions each of which can be coupled to the electrical device to provide operating potential and/or signals thereto or therefrom. The isolated ground plane portions have an impedance less than that of the electrical conductors and provide an alternate means for connecting operating potential(s) and/or operating signals to and from the electrical device while still functioning as a ground plane for the electrical conductors.

Abstract: The contrast of a photoresist layer used in a lithographic process for a given light source is optimized by determining the nonlinear relationship of the photoresist contrast with regard to the thickness thereof and then placing over a substrate a thickness of photoresist corresponding to a desired value of contrast indicated by the nonlinear relationship of contrast with photoresist thickness. The nonlinear contrast with regard to photoresist thickness function is a damped, sinusoidal like function with the difference between maxima and minima contrast values decreasing as the photoresist thickness increases and with higher absolute maxima values for contrast as photoresist thickness decreases.

Abstract: The mold described has walls disposed about the mold plates and vent pin retainer plates to permit a vacuum to be generated. The vent pins have been designed to be self cleaning. A pin having a generally cylindrical shape is used. A first portion of the pin has a face defined by a chord of the cylinder. The face leaves a small space between the pin and the opening wall which permits the atmosphere to be removed from the cavity. Below the first portion is a second portion, smaller in diameter than the first portion. Below the second portion is a third portion of essentially the same design as the first portion rotated 45.degree.. This portion cleans the walls of the opening when the pin is raised to eject the parts.

Abstract: A mounting beam is described having a V-shaped surface capable of having various sizes of semiconductor crystals mounted thereon. This mounting beam is comprised of either: a graphite material mixed with aluminum oxide or silicon carbide; or a graphite body having dressing sticks disposed therein. During the slicing process, when a slicing blade cuts through the crystal into the mounting beam, the blade will be dressed by the sticks or the mounting beam itself.

Abstract: A steering module assembly having a contoured housing unit to receive a PC board which has soldered to it a plurality of optoelectronic devices wherein neither said plurality of optoelectronic devices nor said PC board come in direct contact with the housing unit. The PC board also has a saddle element which contains snap retainers to receive each of said plurality of optoelectronic devices. A fitted cover encloses the housing unit.

Abstract: An automatic gain control circuit (e.g. for use in a SECAM television receiver) comprising: an input node (2); an output node (40); controllable gain amplifier means (6) having a signal input (4) connected to the input node, a control input (24) and an output (8); automatic gain control means (20) having an input (18) coupled to the output of the controllable gain amplifier means and an output (22) connected to the control input of the controllable gain amplifier means; and divider means (30) having a first signal input (28) coupled to the output of the controllable gain amplifier means, a divide signal input (36) coupled to the input of the automatic gain control means and an output connected to the output node of circuit, whereby the signal produced at the output of the divider means is substantially independent of the signal level produced at the output of the controllable gain amplifier means.

Abstract: An improved vertical sync separator for a TV receiver includes an integrator circuit that comprises a current mirror one current path coupled to a normally conducting semiconductor element to discharge a capacitor and another current path coupled to a signal receiving semiconductor element to charge the capacitor. The output of the integrator circuit is coupled to an amplifier having a slicing level that varies with the strength of the received signal.

Abstract: A variable slicing level is provided for the sync pulse separator of a television (TV) receiver to enable proper sync signal separation from the video signal as the strength of the received signal changes. The automatic gain control (AGC) signal is used to vary the conduction of at least a single additional transistor to move the slicing level toward or away from the sync pulse tip depending upon the strength of the received signal.

Abstract: A TV receiver having a single vertical sync counter is combined with various gates and a latch circuit to provide two modes of operation. In the first mode of operation, the vertical counter counts up to a first predetermined number of pulses at which time the counter is automatically reset. In the second mode of operation the counter is counted up to a second predetermined number of pulses which is greater than the number of pulses in the first mode before automatically resetting. The two modes of operation enable the TV receiver to readily operate in TV systems having different number of lines per picture.

Abstract: The maximum current flow in a circuit is limited to a predetermined maximum value by dividing the load current into low and high current paths with the use of interconnected current mirror circuits. By limiting the current flow in the low current path by means of a low current constant current source, the maximum value of a much larger current flow through the load is limited to a predetermined value.

Abstract: A bit switch for use in a digital-to-analog converter comprises three differential pairs of transistors. The first pair receives a digital input signal and a reference voltage signal. The second pair switches the bit current to either an output bus or to ground depending upon the state of the input signal. A third differential pair of transistors is coupled between the first and second pairs for minimizing adverse effects of fast input transitions and parasitic capacitance.