Abstract: In a data processing system, a method for performing register renaming with back-up capability. A register renaming apparatus (18) comprises a logical-physical (LP) register map (30), a free list (32), and an internal swap bus (90) for exchanging information between the two. The register renaming hardware (18) is connected to an instruction sequencer (12) and instruction decode/issue logic (16). Each time the decode/issue logic (16) decodes an instruction(s), the logical registers to be read index the LP map (30) to find the physical register "name" where their values can be found. The free list 32 is indexed by instruction slot numbers. Each free list cell (60-75) contains two physical register names a "last" and a "current", as well as pointer (80-83) designating which name is "current". As each write is done the "current" name is transferred to the LP map 30, and the previous physical register name in the LP map (30) is installed in the free list (32) in the place of the "last" name.

Abstract: A method and apparatus for implementing a power-up state initialization. A power sense circuit provides a signal for indicating when the power supply, V.sub.DD, is of a voltage level greater than the minimum voltage level suitable for safely resolving CMOS logic. The power sense signal, when asserted, enables a small, on-chip ring oscillator. An output signal generated by the ring oscillator supplies a clocking signal to the clock drivers and to the clock state machine of the CPU, thereby providing internal clocks to a central processing unit (CPU). A counter counts the number of clock pulses provided to the CPU and disables the ring oscillator and the clock state machine (thereby stopping the internal data-processor clock drivers) when the accumulated number of clock pulses equals or exceeds a predefined number. The predefined number of internal clock pulses is the minimum number of clocks to process a reset condition that resolves all on-chip, CPU state conflicts and contention.

Abstract: A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forces phase alignment of a reference clock signal to the DCO (16) output and then counts the number the DCO (16) output pulses occurring during a reference clock period. The reference clock signal enables the DCO (16) on one signal transition and detects the presence of an oscillator counter (52) output on the same reference clock signal transition, but one reference clock period later. A synchronizer (49) is used to pass the counter (52) output to ensure no metastability. The DCO (16) is then disabled to allow frequency adjustments to occur via other circuitry.

Abstract: A data processing system (10) and method for performing a snoop-retry protocol using an arbiter (14). Multiple bus masters (12, 16, 17) are coupled to multiple shared buses (20, 22, 24, 26). Each bus master (12, 16, 17) may initiate a bus transaction ("initiating master"), or snoop the bus transaction ("snooping bus master") occurring on a shared bus (20). When an initiating processor requests access to a dirty cache line in a memory (18), a snooping bus master asserts a shared address retry (ARTRY*) signal to inform the initiating processor to relinquish ownership of the shared bus (20) and retry the bus transaction. Upon detecting the shared ARTRY* signal, all potential bus masters remove their bus requests and ignore any bus grants from the arbiter (14), thus allowing the snooping processor which asserted the ARTRY* signal to gain ownership of the shared bus (20) to perform the snoop copyback.

Abstract: A method and apparatus for performing frequency acquisition. Frequency acquisition is accomplished by utilizing binary-search techniques with a controller (13), variable digital oscillator (16), frequency detector (11) an incrementor (19) and decrementor (21) and control registers (22). The frequency detector (11) generates an output indicating the relative speed of the variable oscillator (16) with reference to a externally provided signal. Depending on the output of the frequency detector (11 ), the arithmetic logic circuitry (19, 21) will increase or decrease the value in a control register (22), resulting in a corresponding increase or decrease in speed of the variable oscillator (16). The magnitude of changes to the control register (22) is gradually reduced as the steps of frequency detection and arithmetic updates are repeated until the variable oscillator (16) has reached the proper frequency.

Abstract: A method and apparatus for performing, after frequency acquisition, phase acquisition and phase maintenance in a digital phase-locked loop 10. A phase detector (12), determines the phase relation of an oscillator output to a reference clock signal, and provides a control signal to a controller (13), indicative thereof. When a subsequent logic state of the control signal provided by the phase detector is equal to an initial logic state of the control signal, the controller (13) increments or decrements a control value initially corresponding to a baseline frequency of the oscillator by the gain value, based upon the logic state of the control signal. When the control signal changes state, phase-lock has been acquired, and a gain value which determines the magnitude of change of the oscillator frequency is decreased. On every subsequent change in the logic state of the control signal, the gain value is decreased, unless at a minimum.

Abstract: A method and apparatus for implementing a constant gain in a digitally-controlled variable oscillator (DCO) 16 where the frequency of the DCO 16 is controlled via binary-weighted control signals. The frequency of the DCO 16 is modulated via arithmetic increments or decrements to the binary-weighted DCO control signals. The magnitude of the arithmetic increments and decrements defines the gain of the DCO. To maintain a constant gain, regardless of operating point or environment, a phase gain register 15 bit-shifts a current DCO control value by a predefined number of bit positions, thereby determining a phase gain value. The phase gain value defines the magnitude of an arithmetic increment or decrement of the current DCO control value, used to determine the next DCO control value. Since the phase gain register 15 uses a bit-shifted version of the current value of the DCO control, the gain value dynamically tracks all updates to the DCO control value, thereby implementing a constant gain in the DCO 16.

Abstract: A data processing system (10) and method for performing bus arbitration protocol using an arbiter (14). The data processing system (10) has multiple bus masters (12, 16) each of which is coupled to multiple shared buses (20, 22, 24, 28). The arbiter (14) detects a bus request from a requesting bus master, and responds with a bus grant to notify the requesting bus master that the arbiter has selected the requesting bus master to be a bus-master elect for a shared bus (20). The requesting bus master monitors a shared signal line to determine when a current bus master has released ownership of the shared bus (20). When the requesting bus master assumes ownership of the shared bus it deactivates the bus request signal for a dock period after commencement of the bus transaction, which allows the arbiter (14) to select a next bus master-elect, thereby preventing any bus master from monopolizing the shared bus (20).

Abstract: A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache set or as a static random access memory (SRAM) bank. Based upon the configuration of the set, the tag store array (58) is used for storage of actual data, in the SRAM mode, or for storage of a set of tag entries in the cache mode. A module configuration register (40) specifies the mode of each set/bank. A set of base address registers (41-44) define the upper bits of a base address of SRAM banks. In SRAM mode, comparison logic (66) compares a tag field of the requested address (50) to the base address to determine an access hit. The least significant bit of the address, tag field is used to select either the tag store array (58) or the line array (60) for the requested address data read or write.

Abstract: An all digital phase lock loop (ADPLL), (10) includes a variable digital oscillator (DCO 16), a phase detector (12), a controller (13) including an incrementor (19) and decrementor (21), and a set of oscillator control registers (22). A frequency tracking circuit (20) is separated from the phase acquisition/maintenance logic circuitry. The frequency tracking circuitry (20) uses an anchor value to maintain and update a DCO control value corresponding to a target frequency of operation of the DCO (16). Updates to the anchor value are facilitated by monitoring recent history of an output control signal (ahead or behind) provided by the phase detector (12). The anchor value is changed to maintain the target frequency of operation of the DCO (16), even in the presence of variations in operating environments.

Abstract: A method and apparatus for performing prenormalization during execution by an execution unit (100) of a floating-point add/subtract operation using two data operands. The execution unit (100) adds a mantissa portion of a first and a second floating-point data operand to generate a prenormalized mantissa sum. The execution unit (100) minimizes critical path delays to allow high-performance floating-point calculations while simultaneously reducing logic. Instead of treating the prenormalized mantissa sum as a 64-bit value with special treatment in case of a carry out due to overflow, the floating-point adder 100 treats the prenormalized mantissa sum as a 65-bit value, with the most significant bit being a carry output. Instead of conditionally incrementing an initial exponent value, the initial exponent value is always incremented. Thus, allowing the floating-point adder unit 100 to perform the exponent adjustments for normalization and for rounding faster.

Abstract: A data processor (10) has a floating-point execution unit (32) for executing a floating-point compare operation using two data operands. The execution unit (32) uses mantissa comparator logic (107) to perform a bit-wise comparison of a mantissa portion of a first operand with the mantissa portion of a second operand, and to provide a mantissa comparison result. Similarly, exponent comparator logic (122) performs a bit-wise comparison of an exponent portion of the first operand with the exponent portion of the second, and provides an exponent comparison result. Comparator logic (114) in the execution unit receives the mantissa comparison result and the exponent comparison result. If the exponent portions of the two operands are not equal, the comparator logic (114) uses an operand sign bit of each operand and the exponent comparison result to order the two operands.

Abstract: A data processing system is provided which has more general purpose physical registers than architectural (logical) registers. The data processing system uses a register inventory system to monitor the allocation state changes of each of the physical registers in a register file. As a sequencer issues instructions, an indexed random access memory (RAM) stores a copy of visible and allocation state bits for each of physical registers. When the sequencer needs to perform a branch repair, the sequencer must back up to the checkpoint where the branch instruction was issued. The visible and allocation bits for each physical register at this checkpoint are read out of the RAM. Using the information read from the RAM, and a predefined back-up deallocation relation, the register inventory system determines which physical registers to deallocate and returns those physical registers to a free pool for future allocation.

Abstract: A sequential prefetch method is provided for a pipelined data processor having a sequential instruction prefetch unit (IPU). An instruction queue in the IPU is coupled to a pipelined instruction unit and an instruction cache of the data processor. A prefetch controller in the IPU keeps the instruction stream prefetched so that the instruction queue may load any combination of one, two, or three word instructions into the pipelined instruction unit every clock cycle. The pipelined instruction unit receives instruction words from the instruction queue, and decodes the instruction for execution operations, and for the instruction length/pipeline movement. A queue filling method is provided for maintaining the requisite number of instruction words in the instruction queue to avoid pipeline stalls. The queue filling method is based upon the movement of the instruction pipeline attributable to the usage by an instruction sequencer of the instruction words received from the instruction queue.

Abstract: A method for servicing peripheral interrupt requests in a data processing system is provided. A state vector register stores a current state of a state machine which controls the interrupt-generating peripheral. In addition, the state vector register simultaneously stores an interrupt source identifier, which indicates the source of the highest priority interrupt request currently pending for the interrupt-generating peripheral. When the processor receives an interrupt request, the value stored in the state vector register of the interrupt-generating peripheral is read into an index register in the processor. The processor then uses the value as an index into a jump table, stored in memory, which contains the interrupt service routines. The use of the state vector register in conjunction with existing internal signals enables the processor to rapidly retrieve the appropriate interrupt service routine from memory, while minimizing the system overhead associated with servicing the interrupt request.

Abstract: A carry look-ahead (CLA) adder accommodates a late carry-in from a low-order external 32-bit adder to enable a 96-bit addition to be performed in the same time in which the CLA adder (60) performs a 64-bit addition. Within each adder slice, intermediate group propagate and group generate terms are generated for each bit location in the adder (60), while the adder simultaneously generates an n-bit group propagate and group generate term. The intermediate group propagate and group generate terms are combined with carry-in terms to generate, in parallel, local carry-out terms within each adder slice. The local carry-out terms and intermediate group propagate and group generate terms are used to form a carry chain path which allows the adder to delay the carry-in of an external carry term.

Abstract: A method and apparatus for performing integer and floating-point divide operations using a single modified SRT divider in a data processor. The floating-point and integer division is performed using SRT division on normalized positive mantissas (dividend and divisor). Integer division shares portions of the floating point circuitry, however, the sequence of operations is modified during the performance of an integer divide operation. The SRT divider performs a sequence of operations before and after an iteration loop to re-configure an integer divisor and dividend into a data path representation which the SRT algorithm requires for floating-point mantissas. During the iteration loop, quotient bits are selected and used to generate intermediate partial remainders. The quotient bits are also input to quotient registers which accumulate the final quotient mantissa. A full mantissa adder is used to generate a final remainder.

Abstract: A method for performing graphics Z-compare and pixel merge operations, for use in a Z-buffering system to remove hidden surfaces when displaying a three-dimensional image, is provided. The data processing system includes a main memory for storing data and instructions, and a graphics execution unit for executing graphics instructions. The graphics execution units are connected to an instruction sequencer, which provides instructions and data operands to the execution units, via a communications bus. In response to receiving Z-compare and pixel merge instructions, the graphics execution unit compares one or more Z-axis coordinates within a first data operand to one or more Z-axis coordinates in a corresponding bit-field position within a second data operand to determine a relative Z-axis position of each of the one or more pixels associated with the one or more Z-axis coordinates.

Abstract: A Wallace tree multiplier array (40) performs multiply operations using operands received via a data path (42) having a predetermined height. Rows of carry save adders (CSAs 15'-19") add sets of partial products to generate sets of intermediate summands, which are recursively added to generate a set of final summands. A first group of CSAs form a column which is placed along an axis parallel to the data path (42), and are used to compute a more significant number of bits of each of the summands. The column height of the first group of CSAs is equal to and aligned with the height of the data path (42). A second group of CSAs are placed along an axis perpendicular to the column formed by the first group of CSAs, thereby minimizing the dimension of the multiplier along the data path. The second group of CSAs compute a less significant number of bits of the summands.

Abstract: In an integrated circuit microprocessor, an M-bit priority encoder circuit indicates the highest priority bit position that is set in a first portion of an N-bit (N generally being greater than M) data word and provides control information regarding the number of bits that are set. If more than one bit is set, the highest priority bit is reset, the first portion is re-analyzed, and highest priority bit information and control information are again provided. If only one bit or no bit is set in the first portion, a second portion is analyzed, and highest priority bit information and control information regarding the second portion is provided. Analysis of the second portion, and of any subsequent portions, continues in similar fashion until no further bit positions are determined to be set in the data word.