Abstract: An apparatus for lifting and lowering a toilet seat assembly includes a motion sensor, a motor assembly, a first gear located on a shaft of the motor, a second gear interfaced with the first gear, a drive shaft interfaced with the second gear. A lever is coupled to the drive shaft for lifting the toilet seat. The apparatus may include a bearing housing that includes a movable lead screw with a detent. A first end of a first spiral spring is connected to a slot of the drive shaft within the bearing housing. The first spiral spring is wrapped around the drive shaft. A second end of the first spiral spring is located in a path of the detent. The hubs of the second gear and the drive shaft may be connected together using a crank shaft. A microcontroller may control the motor assembly and be programmable using the sensor.

Abstract: A nonvolatile memory device that includes first and second storage areas, and a control logic configured to control the first and second storage areas, wherein when a program operation of the first storage area is passed before a program operation of the second storage area is passed, the control logic completes the program operation of the first storage area and continues the program operation of the second storage area is provided.

Abstract: A method of operating an image pickup system includes generating a first control signal in response to a long duration exposure mode selectively input by a user, setting circuits to process image data associated with modes other than long duration exposure mode to a standby mode in response to the first control signal, generating a second control signal when the standby mode has been established, opening a shutter in response to the second control signal, and performing a long duration exposure to accumulate a charge corresponding to an optical signal incident on an image sensor of the image pickup system when the shutter is open.

Abstract: A system and method are provided for automatic dose-correction recipe generation, the system including a dose-correction recipe generator, a reticle data unit in signal communication with the recipe generator, a slit data unit in signal communication with the recipe generator, a process data unit in signal communication with the recipe generator, a wafer data unit in signal communication with the recipe generator, a control unit in signal communication with the recipe generator, and an output unit or a storage unit in signal communication with the control unit; and the method including receiving a current reticle data set and a previous reticle data set, receiving a current slit data set and a previous slit data set, receiving a process condition, receiving a wafer condition, automatically generating a dose-correction recipe in accordance with the received reticle, slit, process and wafer information, and controlling a dose in accordance with the generated recipe.

Abstract: A method and apparatus for generating a low reference voltage having low power consumption characteristics is provided. A reference voltage generating apparatus includes a constant current source circuit which generates a reference current. A load circuit is connected to the constant current source circuit and generates a voltage which is proportional to the reference current. A current branch circuit removes a portion of temperature-invariant current components included in the reference current from a connection terminal of the constant current source circuit and the load circuit to a ground terminal through a current branch which is different from a current branch of the load circuit.

Abstract: An apparatus for etching an edge of a wafer includes a chamber, a chuck disposed inside the chamber upon which the wafer is disposed, a plate spaced apart from the wafer and disposed above the wafer, and an edge ring formed along the edge of the wafer and combined with an outer periphery of the plate, wherein the edge ring comprises a ring base spaced a distance apart from the wafer to form a parallel plane with respect to the wafer, and a first ring protrusion protruding from the ring base to insulate the edge of the wafer from a central region of the wafer.

Abstract: A method for facilitating governmental lottery play over television includes receiving a lottery ticket purchase request from a player terminal including a television over a television service provider communication network. Personal information pertaining to a player is retrieved from a subscriber database of the television service provider. It is then verified that the player satisfies predetermined criteria based on the retrieved personal information. The purchase of a lottery ticket is processed based on the received lottery ticket purchase request when it is verified that the player satisfies the predetermined criteria.

Abstract: A circuit for generating a reference voltage includes a first reference voltage generating circuit disposed outside a chip and a second reference voltage generating circuit disposed inside the chip. The first and second reference voltage generating circuits output first and second reference voltages to first and second output terminals, respectively. The second reference voltage generating circuit includes at least one pull-up resistor and at least one pull-down resistor. The pull-up resistor is coupled between a first node where an internal power supply voltage is coupled and the second output terminal. The pull-down resistor is coupled between a second node and the second output terminal, wherein a voltage at the second node is relatively lower than a voltage at the first node. A third reference voltage is outputted from a node where the first output terminal is coupled to the second output terminal.

Abstract: A display apparatus includes a display panel, a flexible printed circuit board, a first data driver, and second data driver. The display panel includes a display area in which an image is displayed in response to a data voltage and a peripheral area adjacent to the display area. The flexible printed circuit board is attached to the peripheral area and includes a plurality of flexible circuit lines. The first data driver is mounted on the flexible printed circuit board to directly receive image data through a part of the flexible circuit lines and convert the image data into the data voltage. The second data driver is mounted on the peripheral area to directly receive the image data through a remaining part of the flexible circuit lines and convert the image data into the data voltage.

Abstract: A method of countering side-channel attacks on an elliptic curve cryptosystem (ECC) is provided. The method comprises extending a definition field of an elliptic curve of the ECC to an extension ring in a first field; generating a temporary ciphertext in the extension ring and countering attacks on the ECC; and generating a final ciphertext for the first field if a fault injection attack on the ECC is not detected. The countering of attacks on the ECC may comprise countering a power attack on the ECC. Checking if there is a fault injection attack on the ECC may be performed by determining if the temporary ciphertext satisfies a second elliptic curve equation. The fault detection algorithms takes place in a small subring of the extension ring, not in the original field, to minimize the computational overhead. The method can improve the stability of the ECC and reduce computational overhead of the ECC.

Abstract: A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block.

Abstract: A display device and a driving method of the same are provided. The display device includes a display panel having gate lines and data lines. A gate driver is included in each of stages and supplies each of the plurality of gate lines with gate signals using a clock signal and a clock bar signal. Each of the stages includes a gate output terminal through which the gate signal is outputted, a pull-down unit connected to the gate output terminal that pulls down a level of the gate signal using a first gate-off voltage. A holding unit is connected to the gate output terminal and holds the level of the pulled-down gate signal at a level of a second gate-off voltage using the second gate-off voltage, which is higher than the first gate-off voltage.

Abstract: A method for performing a search for information pertaining to a search subject includes receiving a name of a person. A social/professional value is received. A search is performed based on the received name. A plurality of personal candidates is identified from results of the search and profiles of the same person in different search domains are automatically linked. A search subject is selected from among the identified plurality of candidates based on user input. The search results are characterized along a scale from social information to professional information. The search results are filtered based on the received value indicative of the desired level and the characterization of each item of results found. The filtered search results are displayed.

Abstract: Provided are a timing controller, a liquid crystal display (LCD) driver including the same, and a method of outputting display data, where the timing controller receives a vertical synchronous signal and a data enable signal, generates an internal data enable signal having a period that is longer than the period of the data enable signal in response to the vertical synchronous signal and the data enable signal, and updates a memory using the internal data enable signal; where the LCD driver including the timing controller outputs display data stored in a memory device based on the internal data enable signal; where a data line driving circuit drives data lines based on the output display data; and where the method of outputting display data is performed by the LCD driver.

Abstract: A loudspeaker system includes a speaker enclosure having an opening in a front wall, and a speaker manifold mounted within the speaker enclosure and communicating with the opening. The speaker manifold includes a pair of substantially parallel side walls, a back wall, and top and bottom walls, defining a manifold chamber. The wall opposite the back wall is substantially open to define a manifold opening and to permit the communicating. The manifold opening is substantially in alignment with the front wall opening. A woofer is mounted on a first wall of the speaker manifold. An acoustic vent is mounted on a second wall of the manifold, such that the woofer and the acoustic vent face each other at one of about a 180 degree angle or about a 90 degree angle.

Abstract: A semiconductor memory device capable of reducing current consumption in a partial-array self-refresh (PASR) mode includes a plurality of banks and at least one parity bank. A specific area to be self-refreshed is individually selected from each of some banks selected out of the plurality of banks to perform a self-refresh operation. Data of the specific area to be self-refreshed is verified using an error correction code (ECC) stored in the parity bank.

Abstract: A method for calibrating a phase include comparing a phase of an in-phase output signal and a phase of a quadrature-phase output signal and generating a digital code corresponding to a comparison result, and controlling the phase of the in-phase output signal in response to quadrature-phase differential input signals and the digital code, and controlling the phase of the quadrature-phase output signal in response to in-phase differential input signals and the digital code, to make a phase difference between the in-phase output signal and the quadrature-phase output signal 90°.

Abstract: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.

Abstract: A capacitor includes a substrate, a plurality of first storage electrodes, a plurality of second storage electrodes, a first supporting layer pattern, a dielectric layer and a plate electrode. A plurality of contact pads is formed I the substrate. The first storage electrodes are arranged along lines parallel with a first direction and electrically connected to the contact pads, respectively. The second storage electrodes are respectively stacked on the first storage electrodes. The first supporting layer pattern extends in a direction parallel with the first direction between adjacent second storage electrodes and makes contact with the adjacent second storage electrodes to support the second storage electrodes. The dielectric layer is formed on the first and second storage electrodes. The plate electrode is formed on the dielectric layer.

Abstract: A driving circuit of a data electrode is provided which includes a drive controlling unit, a first driving transistor and a second driving transistor. The drive controlling unit compares a previous data signal and a present data signal in response to an energy recovery enable signal and outputs a first driving signal and a second driving signal, which correspond to the comparison result. The first driving transistor transmits an address driving signal to an output node connected to the data electrode in response to the first driving signal. The second driving transistor transmits a reference voltage to the output node in response to the second driving signal.