Patents Represented by Attorney, Agent or Law Firm Chris A. Caseiro
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Patent number: 5489861Abstract: An output buffer circuit with edge-rate control capable of maintaining both rising and falling edge-rates within narrow specifications in the face of wide variations in load impedance. In particular, the output buffer of the present invention is intended for coupling to a common bus whereby it may be presented with very low resistive impedance loads and varying capacitive loads. The control schemes for both the pull-up and the pull-down parts of the circuit of the present invention utilize in part fixed currents charging a selected capacitance in order to achieve a metering of the charging or discharging current at the buffer's output. For the pull-down part of the circuit a dual MOS/Bipolar pull-down scheme is used, with the MOS transistors sequentially turning on in a gradual fashion so as to smooth the onset of current sinking. Subsequently, after a measured delay, a bipolar pull-down transistor is turned on.Type: GrantFiled: December 20, 1993Date of Patent: February 6, 1996Assignee: National Semiconductor CorporationInventor: Michael J. Seymour
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Patent number: 5482540Abstract: A grid-frame stabilizer and method of operation for an electrostatic precipitator includes a rigid stand-off member that prevents oscillation of a grid frame used to keep discharge electrodes of the precipitator separated from one another. One end of the stand-off member is rigidly connected to the grid frame and the other end is rigidly connected to a fixed housing component through at least one electrical isolator. The fixed housing component is firmly affixed to an interior region of the precipitator. The stand-off member passes into the housing component through a housing opening which is preferably sealed by a membrane designed to prevent particle contamination of the surfaces of the electrical isolators.Type: GrantFiled: January 31, 1994Date of Patent: January 9, 1996Assignee: Castine Energy ServicesInventors: John G. Trinward, John P. Jabar, Jr.
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Patent number: 5459412Abstract: A translator circuit for converting from a first logic-level range to a second logic-level range, as is generally involved in the translation from an ECL stage to a CMOS stage. The translator includes a reference stage that provides a reference voltage that is coupled to the CMOS logic stage as well as the ECL logic stage. The ECL logic stage is indirectly coupled between a high potential power rail and a low potential power rail through a plurality of transistors. The CMOS stage is coupled to the ECL stage through two emitter-follower transistors. The CMOS stage uses current-mirroring techniques in combination with the isolated reference stage to effect a translation from the ECL logic level to the CMOS logic level. The CMOS stage also provides relatively fast propagation time which may be set, within certain limits, to a desired time.Type: GrantFiled: July 1, 1993Date of Patent: October 17, 1995Assignee: National Semiconductor CorporationInventor: Ray A. Mentzer
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Patent number: 5418474Abstract: A transient-eliminating circuit for minimizing simultaneous conduction through the pullup and pulldown transistors of a buffer circuit. In a buffer circuit used to translate logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail, in which the potentials of the two high-potential rails are not equal, the transient-eliminating circuit is coupled between the output stage and the input stage in such a way that the translator can be utilized independent of power-up sequencing and without any static current I.sub.CCt. The transient-eliminating circuit minimizes simultaneous conduction through the pullup and pulldown transistors of the translator by delaying the turn-on of the pulldown transistor until the pullup transistor is completely off.Type: GrantFiled: September 24, 1993Date of Patent: May 23, 1995Assignee: National Semiconductor CorporationInventors: Jeffrey B. Davis, Jay R. Chapin
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Patent number: 5408147Abstract: A circuit for translating logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail in which the potentials of the two high-potential rails are not equal. The translator of the present invention is utilized in the transition from a 3V-supplied circuit to a 5V-supplied circuit, or vice versa, without any static current I.sub.CCt and regardless of the power-up sequencing. The static current is eliminated by isolating the output of the first stage of the translator, which is at the first high-potential power rail level, from all transistors of the second stage that are tied directly to the second high-potential power rail. In the preferred embodiment of the invention the transistors of the second stage that are powered by the second high-potential power rail are PMOS transistors and the isolation is achieved by linking those PMOS transistors to the first stage through a series of controlling NMOS transistors.Type: GrantFiled: September 7, 1993Date of Patent: April 18, 1995Assignee: National Semiconductor CorporationInventors: Roy L. Yarbrough, Jay R. Chapin
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Patent number: 5357640Abstract: A dressing-aid-and-transfer device for assisting attendants and patients in moving and dressing. The device includes a space frame with support legs of the space frame defining a device perimeter. A chest support is provided to support the weight of the patient being moved. The space frame is designed so as to provide a stable and lightweight transferral device that is transportable and easy for a single person to operate. The support legs and reinforcing cross-pieces are configured to provide structurally stability without interfering with an attendant's ability to easily remove and place clothing on a patient's lower body. The support legs pivot at the base of the space frame in order to reduce the force required to transfer a patient to and from a sitting position. Optional features include a rotatable base and the use of actuators to reduce the effort required to tilt the space frame.Type: GrantFiled: November 16, 1993Date of Patent: October 25, 1994Assignee: McKenney GroupInventors: Michael A. McKenney, Daniel McKenney
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Patent number: 5349311Abstract: A voltage controlled oscillator (VCO) operating as a variable length, variable delay, ring oscillator having a current starved inverter and an anti high-gain circuit for each stage. A VCO feedback signal is compared with a reference frequency obtained, for example, from a system crystal oscillator. A phase and frequency detector monitors these two input signals and issues "up" or "down" commands to a digital counter. This digital counter delivers select signals via a decoder and also drives a Digital to Analog Converter ("DAC"). The digital select signal from the counter chooses an operational stage from the multi-stage, tandem-connected VCO. A broadband operation for the VCO is achieved by overlapping the individual frequency ranges associated with each of the individual stages. The DAC moves the operation along each selected frequency range associated with a selected stage until a system lock between the VCO output and the crystal references is achieved.Type: GrantFiled: November 23, 1992Date of Patent: September 20, 1994Assignee: National Semiconductor CorporationInventor: Ray A. Mentzer
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Patent number: 5316324Abstract: A collet-and-shank assembly for gripping a work piece or tool used in rotary cutting equipment. The assembly includes a dual-threaded nut that enables the machine operator to lock and release the device from a single end. The dual-threaded nut is completely recessed within the shank, thereby reducing the overall length of the assembly and increasing the available working space. In the preferred embodiment of the collet-and-shank assembly, the dual-threaded nut has an interior right-hand threading corresponding to the outside threading of a section of the collet. The exterior of the dual-threaded nut has a threading orientation opposite to that of the interior region, corresponding to the threading of an interior section of the shank. When the exterior of the dual-threaded nut is threaded into the shank and the collet is threaded into the interior of the dual-threaded nut, the collet is affixed to the shank, and the work piece or tool is also locked within the collet.Type: GrantFiled: December 28, 1992Date of Patent: May 31, 1994Inventor: Warren E. Hufe. Jr.
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Patent number: 5303646Abstract: A relief printing technique wherein the material to be printed on is placed between an inked relief and a supporting assembly comprising a dressing web and a second relief reproducing the pattern of the printing relief.Type: GrantFiled: January 22, 1993Date of Patent: April 19, 1994Assignee: Melzer Maschinenbau GmbHInventors: Rainer Melzer, Roland Melzer
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Patent number: 5289880Abstract: A towable road tender device for grading unpaved roadway surfaces. The tender device may be hitched to commercial vehicles but is particularly suited for use with private vehicles, such as small tractors and pickup trucks. A set of relatively lightweight frames reduce the weight to be pulled by the vehicle. The towable road tender device is sized to be operated using small-scale power take-off units commonly available in private vehicles, such as, for example, the power units of conventional front-end plows. The set of lightweight frames includes a support frame that secures the tending tool, a wheel frame that pivots the rear towing wheels either toward or away from the support frame, and an attachment frame joining the other two frames to a hitch on the towing vehicle. The attachment frame is designed to keep the support frame parallel to the plane of the underlying roadway surface as that support frame is raised or lowered.Type: GrantFiled: June 3, 1992Date of Patent: March 1, 1994Inventor: Rollin V. Barto
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Patent number: 5268316Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction.Type: GrantFiled: June 12, 1992Date of Patent: December 7, 1993Assignee: National Semiconductor CorporationInventors: Murray J. Robinson, Christopher C. Joyce, Tim Wah Luk
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Patent number: 5150177Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction.Type: GrantFiled: December 6, 1991Date of Patent: September 22, 1992Assignee: National Semiconductor CorporationInventors: Murray J. Robinson, Christopher C. Joyce, Tim W. Luk