Abstract: In order to conduct an electronic reverse auction, a computer system has a post means for posting product description information across a network, a bidding means for submitting a plurality of bids, proposals, and means for transmitting other information about goods and bidders. A means for evaluating the bids by a select criteria and a security means is also provided.

Abstract: A device enables a joystick to be connected to a PS/2® port converts signals from the joystick to mouse-like signals so that neither the software nor the hardware needs to be changed in order to use the joystick instead of the mouse. The directional signals of the joystick are converted to mouse-equivalent signals and discrete signals from the joystick are translated by a device formed and configured to a PS/2® port.

Abstract: A color correlogram (10) is a representation expressing the spatial correlation of color and distance between pixels in a stored image. The color correlogram (10) may be used to distinguish objects in an image as well as between images in a plurality of images. By intersecting a color correlogram of an image object with correlograms of images to be searched, those images which contain the objects are identified by the intersection correlogram.

Abstract: In the present invention, an imaginary aircraft, called the “shadow aircraft,” flies the original flight plan and, in turn, causes the true aircraft to fly the offset course. The offset course has the same number of legs as the original course, and for each leg of the original course, there is a corresponding parallel leg of the offset course. Except for an initial waypoint and a final waypoint, the locations of offset course waypoints are defined to be the intersections of the straight lines parallel to the original legs at the specified offset distance. The range and bearing to the offset course initial waypoint are chosen to be the same as the range and bearing to the next waypoint. For the interior legs of the flight plan, the lengths of the offset course legs vary from the corresponding “true” course leg.

Abstract: A framework for improving program performance by locality-enhancing transformations is presented. This framework is appropriate for modern high-performance machines that have a memory hierarchy. The invention orchestrates the flow of data through the memory hierarchy directly, and is thus able to overcome limitations of existing approaches. This new approach allows for efficient execution of imperfectly nested loop programs which are ubiquitous in numerical calculations and database operations, and it can be integrated into high-performance optimizing compilers.

Abstract: A Web-based video-editing system using a high-performance multimedia software library having a toolkit, the toolkit being a set of reusable, high-performance primitives and abstractions that are at an intermediate level of abstraction between C and conventional libraries. By decomposing common multimedia data types and operations into thin abstractions and primitives, programs written using the toolkit achieve performance competitive with hand-tuned C code, but which are shorter and more reusable. The toolkit programs can employ optimizations that are difficult to exploit in C and are impossible to use in conventional libraries.

Abstract: A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.

Abstract: A SCSI bus extender apparatus coupling a primary SCSI bus to a secondary SCSI bus includes a mechanism for detecting and resolving contention between a substantially simultaneous SELECTION operation on the primary bus and a RESELECTION operation on the secondary bus. The inventive method contemplates the bus extender arbitrating for control of the primary bus after a conflict is detected, and releasing control of the secondary bus if control of the primary bus is obtained. A target device on the secondary bus can then rearbitrate for control of the secondary bus. Once the target device controls the secondary bus, it can direct a RESELECTION signal to the bus extender, which responsively directs the signal to an initiator device on the primary bus. If the bus extender is unable to gain control of the primary bus after a conflict is detected, the SELECTION operation is allowed to proceed and the target device reattempts to assert the RESELECTION operation thereafter.

Abstract: A detachable and replaceable end effector assembly. The detachable mechanism is made of standard end effectors attached to an actuating tip and pinned inside a yoke assembly. Replacement is made by pulling back a spring loaded radial lock 90, to disengage two rear tabs 51 on the outer tip 50. The yoke assembly is then rotated 90 degrees to disengage the rear yoke pin 9 from the tubular shaft 70. This rotation of 90 degrees also unlocks the T-bar 45 from the front "T" slot of the long actuator 80. The end effector or jaw assembly is then free to be pulled away from the remainder of the shaft. In addition there is a bayonet connection to hold the parts together and prevent accidental disconnection.

Abstract: A cooling cap (1) made up with knitted net fabric of polyester yarn comprises an outer open-meshed fabric (3) for covering the front half part of the hemispheric part of the cap to receive the human head, an inner fine linen fabric (4) for lining the outer open-meshed fabric, a water absorbent fiber layer (5) for bearing water or absorbing sweat, and a plurality of eyelets or loopholes (6). The head is cooled owing to the vaporization of the water borne in the water absorbent fiber layer by absorbing the heat.

Abstract: A browser for efficiently browsing large directory trees is presented. The browser uses authentication links as the structure through which the browser navigates. By adhering to the rules for a valid authentication chain, the browser increases efficiency by storing the results of preliminary steps to browsing.

Abstract: The problems of meeting tight latency requirement while keeping network design low in cost and complexity are solved by the present invention of a network controller with a transaction logic block and a descriptor memory. The invention allows the data buffers and the buffer descriptors to be located in two physically separate memory subsystems. Data buffers can reside in a main system memory which are shared by other system clients. The buffer descriptors, which typically require significantly less memory space than data buffers, can reside in a special dedicated memory which can be low cost. The invention provides a method to allow buffer descriptors to be located in a low latency memory, which can be local to the network adapter. The data buffers can be located in a system shared memory. This design allows system shared resources, e.g. main system memory or bus, to be designed with relatively longer delay budget.

Abstract: A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.

Abstract: The variable-level backup scheduling method employs a schedule in which backups are performed at set times but the level of backup performed is determined from the condition of the system at the time of backup. Under this method, user-supplied parameters stored in level-tables allow a determination of the appropriate level of backup to be performed. If the data in the scheduled level of backup has not been modified in a sufficient amount under the supplied parameters, then the backup scheduling method determines whether a specified higher level backup is appropriate. If the evaluation of the higher level backup results in a determination that not enough data has been modified, the next level is evaluated. This process continues until the criteria for backup have been met or the level that has been predetermined to be the least amount of data to be saved has been reached.

Abstract: A dynamic cache resizing mechanism permitting a non-coherent cache memory to be altered in size during the operation thereof. A cache utilization monitoring system determines whether the cache size is optimised for a particular application and environment, and if it is not, modifies a selection process to resize the cache address space. The non-coherent property of the cache is utilized to permit the change of selection process during use, and the choice of selection process may be effected to take into account the proportion of live cache entries which will remain accessible after resizing, and the proportional change in size of the cache during a resizing operation.

Abstract: A software system is defined by a tree of system models which are written in a functional language. During a build of the software system, the functions are interpreted and the results of the expensive expressions are cached. Each function is examined before interpretation to see if it has been evaluated before. If a function has already been evaluated, the cached result is retrieved by the evaluator and the time which would have been spent re-evaluating the function is saved.

Abstract: A Faraday shield minimizes the leakage of electromagnetic interference (EMI) and radio frequency interference (RFI) of a maximum frequency and corresponding wavelength that emanates from electronic components contained within the shield. The top and bottom each contain apertures that are dimensioned to effectively block the escape of EMI and RFI from the shield and to permit the flow of air to dissipate heat without generating acoustic noise. The thickness of the top of the shield is at least one half of the diagonal length across the largest of the apertures located in the top. The length of the longest aperture side is less than one fourth of the wavelength of the maximum frequency of EMI and RFI contained by the shield. Corresponding relationships exist between the apertures located in the shield bottom and its thickness.

Abstract: A method, and apparatus for its use, for reducing the number of disk accesses needed to satisfy requests for reading data from and writing data to a hard disk. A non-volatile cache memory used to hold data blocks for which write requests have been made is purged of "dirty" blocks, not yet written to the disk, based on the proportion of dirty blocks in relation to an upper threshold and a lower threshold. A purge request flag is set when the proportion of dirty blocks goes above the upper threshold, but is not cleared until the proportion of dirty blocks goes below the lower threshold. So long as the purge request flag is set, dirty blocks are purged when the disk is not busy with read requests. Immediate purging is initiated when the write cache becomes totally full of dirty blocks.

Abstract: Postponing the interrupt for an I/O event can increase system throughput by amortizing the cost of the interrupt service routine over multiple I/O events. In current systems that provide interrupt postponement, the time parameter is fixed. Fixed values can lead to parameter configuration errors, excessive characterization work to generate parameter values, and a failure to automatically re-configure to system changes or to external load changes. The proposed mechanism measures actual system experience and eliminates the parameter configuration effort by filtering its own experience to derive a target value for interrupt postponement. A current postponement value with the potentially greater variance than the target is used to rapidly respond to abrupt change in offered load. The invention also benefits tasks with real-time deadlines to provide correct system operation.

Abstract: A device 11 includes a sync unit 20 to identify and achieve synchronization with the cell boundaries of a 53-byte ATM cell stream. Each cell starts with a 5-byte header in which the 5th byte is a CRC byte. Instead of testing all possible bytes to see whether they are cell boundaries, a CRC circuit 21 computes CRCs for successive 5-byte blocks, under the control of a 5-state header counter 22. If such a block is a header, its CRC is a predetermined value, and a match signal is sent to a logic circuit 23, which starts a 53-state cell counter 24 and stops the header counter 22. A 4-state repeat counter 25 checks that the next 5 blocks checked by the CRC circuit 21 are also headers, as confirmation. Synchronization is achieved within at most 5 cells, because the test period of the testing circuitry (which could be longer than the header length) is coprime with the cell length.