Patents Represented by Attorney Christoper P. Maiorana, PC
  • Patent number: 8332801
    Abstract: A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: December 11, 2012
    Assignee: LSI Corporation
    Inventors: Juergen Dirks, Matthias Dinter, Johann Leyrer
  • Patent number: 8125932
    Abstract: A method and apparatus is provided for video conferencing. The method and apparatus continuously receive frames from a plurality of video channels and alternately continuously transmit to each of a plurality of participants in a video conference individual frames containing information concerning each of the video channels. The method and apparatus only transmits at any given instant new picture data for one of the participants in the video conference.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: February 28, 2012
    Assignee: Exedra Technologies, LLC
    Inventor: Chih-Lung Yang
  • Patent number: 8046726
    Abstract: A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs and (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: October 25, 2011
    Assignee: LSI Corporation
    Inventors: Viswanathan Lakshmanan, Michael Josephides, Lisa M. Miller
  • Patent number: 7595453
    Abstract: A surface mount package is provided that includes a first metal layer and a second metal layer configured to be electrically connected to the first metal layer. The surface mount package further includes a ceramic layer between the first and second metal layers. The ceramic layer has an opening therethrough.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: September 29, 2009
    Assignee: M/A-COM Technology Solutions Holdings, Inc.
    Inventor: William Palmteer