Abstract: A health monitoring system includes a plurality of remote user sites, each remote user site comprising at least one health monitoring device for collection of user health monitoring data, an interactive video device, and a user interface apparatus; at least one remote computing facility configured for signal communication with, and to receive health monitoring data-related signals from, the plurality of remote user sites; and at least one computer, configured for signal communication with the remote computing facility, wherein the interactive video device is interactively coupled with the remote computing facility. Associated methods are also described.

Abstract: A method for reduced memory and bandwidth motion adaptive video deinterlacing is disclosed. The method generally includes the steps of (A) generating a frame by deinterlacing a current field in a first of a plurality of modes, (B) generating the frame by deinterlacing using both of the current field and an opposite-parity field in a second of the modes and (C) generating the frame be deinterlacing using all of the current field, the opposite-parity field and another field in a third of the modes, wherein the method uses at least two of the modes.

Abstract: A method of diabetes management, comprising (a) providing a glucose meter in communication with a portable microprocessor-based unit; (b) transmitting blood glucose level data into the hand-held microprocessor-based unit from the blood glucose meter; (c) running a program of instructions on the portable microprocessor-based unit or the glucose meter or both; (d) inputting data based upon the blood glucose level data as input data for the program of instructions; and (e) providing a signal to inject insulin when the blood glucose level data indicates.

Abstract: A method of grounding a heat spreader/stiffener to a flip chip package comprising the steps of attaching an adhesive film to a substrate and attaching a stiffener to the adhesive film. The adhesive film may have a number of first holes corresponding with a number of grounding pads on the substrate. The grounding pads may be configured to provide electrical grounding. The stiffener may have a number of second holes corresponding with the number of first holes of the adhesive film and number the grounding pads of the substrate. The grounding pads are generally exposed through the first and the second holes.

Abstract: A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.

Abstract: A method for decoding a bitstream comprising the steps of (A) generating a first field picture in response to a frame picture of a first bitstream, (B) generating a second field picture in response to the frame picture of the first bitstream and (C) generating a second bitstream containing the first field picture and the second field picture.

Abstract: A health monitoring system includes a plurality of remote user sites, each remote user site comprising at least one health monitoring device for collection of user health monitoring data, an interactive video device, and a user interface apparatus; at least one remote computing facility configured for signal communication with, and to receive health monitoring data-related signals from, the plurality of remote user sites; and at least one computer, configured for signal communication with the remote computing facility, wherein the interactive video device is interactively coupled with the remote computing facility. Associated methods are also described.

Abstract: An apparatus includes an antenna (e.g., a monopole), a first load, and a second load. The antenna, which extends substantially along an axis, has a first end and a second end. The first load is coupled to the antenna at the first end, while the second load is coupled to the antenna between the first end and the second end. Both the first and second loads are symmetrical with reference to the axis. The apparatus is arranged to operate in at least two frequency bands, such as the AMPS band from about 824 MHz to 894 MHz and the PCS band from about 1850 MHz to 1990 MHz.

Abstract: An arbitration logic including one or more modular priority encoders. Each modular priority encoder includes a first logic circuit, a comparator circuit, a second logic circuit, and an encoder circuit. The first logic circuit may be configured to generate a first output signal in response to a plurality of request signals. The comparator circuit may be configured to compare all possible pairs of a plurality of priority signals. The second logic circuit may be configured to generate a control signal in response to (i) the plurality of request signals and (ii) a result of comparing all possible pairs of the plurality of priority signals. The encoder circuit may be configured to generate a second output signal in response to the control signal.

Abstract: An apparatus having a buffer and a circuit is disclosed. The buffer may be configured to receive a digital image. The digital image generally has (i) a Bayer color representation and (ii) two initial dimensions in a horizontal direction and a vertical direction respectively. The circuit may be configured to generate a resample image in a signal by down-sampling the digital image in the Bayer color representation such that (i) the resample image has two resample dimensions, (ii) at least one of the resample dimensions is smaller than a respective at least one of the initial dimensions and (iii) the respective at least one initial dimension is a non-integer multiple of the at least one resample dimension.

Abstract: A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an active edge, (B) calculating a value of a time difference between the latest transition and the active edge, (C) calculating a delay between the active edge and the latest transition appearing in an output signal, wherein (i) the delay is based on a model responding to the value, (ii) the model characterizes a clock-to-output delay as a function of the time difference and (iii) the characterization covering a range of values, (D) calculating an arrival time of the latest transition at a second flip-flop through a second signal path and (E) storing the arrival time in a recording medium.

Abstract: An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data in a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.

Abstract: A method for motion adaptive video deinterlacing is disclosed. The method generally includes the steps of (A) in a first plurality among a plurality of modes, generating a frame by deinterlacing a current field using a plurality of memory bandwidth configurations and (B) in a second plurality among the modes, generating the frame by deinterlacing the current field using a plurality of linestore configurations.

Abstract: An apparatus having a first circuit, a second circuit and a third circuit. The first circuit may be configured to (i) demultiplex a multimedia stream having one or more video and audio streams and (ii) generate one or more video signals and one or more audio data signals in response to demultiplexing the multimedia stream. The multimedia stream may be independent of embedded time stamps. The second circuit may be configured to (i) decode the one or more video data signals and the one or more audio data signals and (ii) generate a video current time signal for each decoded video signal and an audio current time signal for each decoded audio signal. The third circuit may be configured to synchronize the playback of each decoded audio signal and each decoded video signal with the video current time signal and the audio current time signal.

Abstract: An apparatus including a test circuit, an output circuit and a control circuit. The test circuit may be configured to generate test data in response to one or more test vectors. The output circuit may be configured to present data in a first mode and prevent presentation of data in a second mode. The output circuit may be configured to switch between the first mode and the second mode in response to a control signal. The control circuit may be configured to generate the control signal according to predetermined criteria for protecting secure data within the apparatus while allowing the test data to be presented.

Abstract: A communications receiver may include an adaptive filter unit for removing coherent interference components from a received signal. In the absence of a signal of interest, the filter may adapt dynamically to remove current interference components. When a signal of interest is detected, the filter may be controlled to stop (or at least reduce) its adaptation, to prevent removal of the signal of interest. The received signal may be down-converted to a complex baseband by conditioning circuitry. A detector may detect the signal of interest, and control the filter. Autocorrelation may be used to estimate a characteristic of the signal of interest in the complex baseband. The detector may include hysteresis to react quickly to the start of signal of interest, and more slowly to an end of the signal of interest. The signal of interest may be a frequency shift keyed (FSK) signal. A demodulator may demodulate FSK components based on the autocorrelation result.

Abstract: A method for configuring a storage array, comprising the steps of (A) checking a syntax of an input file, (B) generating an error if a particular syntax is not met, (C) determining whether a physical hardware configuration matches a desired set of design parameters, (D) generating a script file containing a plurality of symbol commands, (E) sending the script file containing the symbol commands to the storage array and (F) verifying whether the physical hardware configuration is valid.

Abstract: An apparatus for a guitar comprising a first compressible member, one or more spacers and a second compressible member. The second compressible member may be configured to receive the one or more spacers and engage the first compressible member when a force is applied to the first compressible member.

Abstract: A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.

Abstract: A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.