Abstract: The present invention concerns a circuit comprising a memory array having a plurality of wordlines and a plurality of bitlines, a reference circuit, a column select circuit, an enable control circuit, and one or more sense amplifiers. The reference circuit may be configured to present a reference voltage signal in response to (i) a dummy wordline and (ii) a virtual ground signal, where the dummy wordline may be synchronized with each of the plurality of wordlines. The column select circuit may be configured to present the virtual ground signal in response to a column select signal. The enable control circuit may be configured to present an enable signal in response to the dummy wordline. The sense amplifiers may be configured to generate an output in response to (i) the enable signal, (ii) the reference signal and (iii) the bitlines.