Patents Represented by Attorney Chuck C. Krawczyk
  • Patent number: 4675548
    Abstract: A transistor-transistor logic gate circuit arrangement for saturation control while providing TTL input and output compatibility. The circuit comprises a resistor divider network coupled across the base emitter junction of a phase splitter transistor. A preselected fraction of the phase splitter's V.sub.BE is produced at the base of an antisaturation transistor. The antisaturation transistor is coupled across the collector-base of an output transistor thereby providing a method of clamping an output transistor using V.sub.BE as a reference voltage. Because V.sub.BE is used as the reference, the circuit can maintain TTL output voltage levels while preventing the output transistor from saturating in an extremely wide range of operating temperatures.
    Type: Grant
    Filed: November 13, 1984
    Date of Patent: June 23, 1987
    Assignee: Harris Corporation
    Inventor: Kevin S. Eshbaugh