Abstract: A vector editor for providing an integrated circuit datapath layout. For one aspect, vectors may be extracted from an integrated circuit design input file using a name-based vector extraction approach, a bus/connectivity-based vector extraction approach or another approach. Each vector may be represented as one of a row and a column, wherein the representation differs from that of the associated physical layout. Each bit slice associated with the integrated circuit layout is represented in an orthogonal manner to the vectors. For one aspect, instances of similar master cells may be represented using similar visual representations.

Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.

Abstract: In one embodiment of the invention, a performance information associated with a processor is read. A processor performance table that corresponds to the performance information is located. The performance table includes a plurality of performance parameters to control performance of the processor. A performance state (PS) structure is updated using one of the processor performance table and a default table.

Abstract: A method for filtering requests in portable devices is described. Nonvolatile flash memory is used to store allowable client addresses. The discovery, service discovery, and connection filter algorithms reduces power and processing bandwidth required from portable, mobile devices.

Abstract: Methods and apparatus to control power state transitions in embedded systems are disclosed. In a disclosed method, power state transitions of agents in the system are managed by a central authority. The agents register themselves with the central authority. When a request to transition the system to a requested power state is received, the central authority issues callback instructions to the agents in the system that support the requested power state. The callback instructions are issued in a temporal order indicated by the power state dependencies of the agents. Thus, the central authority arbitrates the order in which the agents transition to the requested power state. The power state dependencies of the agents are registered with the central authority by the agents either at power-up of the system or when the agents are plugged into the system.

Abstract: A high frequency data transmission circuit including design for testability (DFT) features. An integrated circuit includes core control logic to provide a data signal and output drive logic including a local data latch and a transmitter. The data latch receives the data signal and provides true and complementary forms of the data signal to the transmitter over symmetrical signal paths. The transmitter provides an output signal to an external receiver.

Abstract: A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Abstract: In one embodiment of the invention, a system management interrupt (SMI) handler is invoked in response to an SMI. The SMI handler determines a thermal state of a processor. The SMI handler interacts with one of a speed step technology applet and a thermal driver in a thermal management operating system to transition the processor to one of a low power state and a high power state based on the thermal state according to a native performance control status.

Abstract: A clock duty cycle correction circuit. The duty cycle correction circuit is provided at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.

Abstract: A double-edge-triggered flip-flop scan cell. The double-edge-triggered flip-flop scan cell provides the capability to capture and output data for each edge of a clock signal in a functional mode of a host integrated circuit. In a test mode, the double-edge triggered flip-flop scan cell enables test data to be scanned into and out of the scan cell to provide observability and controllability of the scan cell internal state.

Abstract: An integrated circuit device includes dedicated memory verification logic to compare data read from a set of cells in a memory at a first time to data read from the same set of memory cells at a second time.

Abstract: An integrated circuit device interconnect with controlled inductance. An integrated circuit device includes an insulating layer formed on a substrate and a an interconnect disposed on the insulating layer extending along a first path. A dedicated current return path having one end configured to be coupled to ground is disposed on the first insulating layer parallel to the interconnect, such that the signal received by the interconnect is returned to ground via the dedicated current return path when the dedicated current return path is coupled to ground. Inductance of the interconnect is thus controlled by reducing the area of the circuit loop formed by the interconnect and the parallel dedicated current return path. In one embodiment, the dedicated current return path is formed in an embedded ground plane just above or below the first interconnect.

Abstract: A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately.

Abstract: Integrated counter-based instrumentation for generating a frequency distribution representation such as a histogram. An integrated circuit device includes an event counter to count a number of a predetermined type of events detected in each of a plurality of measurement periods during a first sub-experiment period. A frequency counter coupled to the event counter is to be incremented at the end of each measurement period if the number counted by the event counter meets a first test. A count stored in the frequency counter is provided to a frequency distribution data store at the end of the first sub-experiment period.

Abstract: A memory device. The memory device includes a nonvolatile memory array including a first block of memory cells. A first volatile protection bit coupled to the first block is programmable to prevent a memory access operation directed to the first block from being performed.

Abstract: An integrated circuit device package. The package includes a package substrate having a conductive bondring disposed thereon. A via is electrically coupled to the bondring. A conductive bondring extension is also disposed on the package substrate. The bondring extension is electrically coupled to the bondring and the via and extends away from the bondring and the via.

Abstract: A bus utilization detection circuit and method. An input is configured to be coupled to a bus to detect bus events. A circuit coupled to the input determines a number of bus events during a first sample period to indicate a percent bus utilization. If the number of bus events during the first sample period meets a first predetermined threshold value, then an activity event is generated. In another embodiment, an activity event is generated only if during a second sample period, the number of first sample periods for which the percent bus utilization meets the first threshold value meets a second threshold value.

Abstract: A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first unprogrammed resistance.

Abstract: A high-sensitivity fuse-based storage cell. A first circuit branch including a first fuse is coupled to a second circuit branch including a second fuse in a current mirror configuration. An output node is coupled to the first circuit branch and responsive to a sense enable signal to indicate a logical "1" if the first fuse is programmed and the second fuse is unprogrammed or a logical "0" if the first fuse is unprogrammed and the second fuse is programmed.

Abstract: An apparatus for dissipating heat transferred to a circuit board. A board on which to mount an electronic device includes a conductive layer. A first board heat dissipation element is thermally coupled to the conductive layer and extends away from a surface of the board to dissipate heat from the conductive layer to the ambient.