Abstract: A reliable fault-tolerant I/O controller supporting redundant synchronous memories is described. The I/O controller includes multiple I/O control logic units where each I/O control logic unit is in communication with a host server and external peripheral devices. Each I/O control logic unit includes a processor, a memory, and a memory controller. A master I/O control logic unit services I/O transactions from the host server and the external peripheral devices. A slave I/O control logic unit operates in a quiescent state until the master I/O control logic unit experiences a memory failure. At such time, the slave I/O control logic unit resumes operation of the I/O controller. In order to facilitate the switchover from the master I/O control logic unit to the slave I/O control logic unit, the master memory controller performs concurrent memory write operations in both the master and slave memories.

Abstract: A timeout mechanism that can accommodate an improved accuracy in determining the timeout of a pending transaction while conserving the amount of processing circuitry is herein disclosed. A fetch state machine is associated with each cache line. When the cache line is fetched from memory, the fetch state machine tracks the number of timeout periods that lapse before the cache line is retrieved. If a predetermined number of timeout periods lapses before the cache line is retrieved, a timeout occurs and processed accordingly.

Abstract: A snapshot mechanism that includes an apparatus and method for tracking DMA read requests for cacheable data that can be altered before the data is returned to a requesting I/O device is herein disclosed. Attributes that uniquely identify the original I/O device and DMA read request are stored in a cache tag unit. A read lock is set when a request is made to obtain the requested data when it is not resident in a local cache. When the cache line containing the requested data is snooped out and the read lock is set, then the cache line is set in a snapshot state. The snapshot state assures that only the original I/O device receives the read data when it has been altered subsequent to the time the original DMA read request was made. Once the data is returned to the original I/O device, the cache line is invalidated in order to prevent another I/O device from reading the stale data. Prefetched data is marked as such and cannot be marked as snapshot data.

Abstract: A mechanism that includes an apparatus and method for accessing a segment of data from main memory that less than the size of a cacheline is herein disclosed. I/O devices connected to an I/O bridge unit having one or more caches make DMA read and write requests for sub-cachelines of data that are less than the cacheline size.

Abstract: An anti-tip device for a computer tower chassis. The anti-tip device includes a hub and a base foot that is mounted to the bottom surface of a tower chassis. The hub is fitted into an interior cavity of the base foot and provides the base foot with a foundation around which the base foot rotates. The hub itself is mounted to the tower chassis through a set of pins that ensure that the hub is kept stationary. The base foot includes an elongated foot and cavity for housing the hub. The interior circumference of the cavity includes a number of detents that define positions of the base foot. The hub includes a spring mechanism including a knob that is fitted to snap into a detent. As the base foot is rotated, the rotational force decompresses the spring so that it rides on the outer surface of the interior circumference of the base foot.

Abstract: An improved technique for incrementally updating a source code representation having cloned variable name definitions to static single assignment (SSA) form is described. The technique receives an intermediate representation of a source program in non-SSA form having one or more cloned variable name definitions that correspond to an original variable name. All the original variable names and their corresponding cloned variable names are collected. An iterative dominance frontier set for those nodes containing a cloned variable name definition or an original variable name definition is formed. This iterative dominance frontier set is then used to determine the nodes in which a single phi-function is inserted for each original variable name. Each use of an original variable name is changed to the cloned variable name that reaches the use. The arguments of the inserted phi-functions are then updated with the cloned variable names that reach the inserted phi-functions.

Abstract: A mechanism that automatically configures the manner in which interrupt signals are shared in order to avoid system failures and improves the system performance is herein disclosed. The mechanism executes as part of the system BIOS during system initialization or reset. The mechanism utilizes information found in the configuration register space to determine the characteristics of the device. The device characteristics are used to determine which devices share IRQ signals. In this manner, devices that cause system failures due to sharing interrupt signals are not assigned a common interrupt signal thereby minimizing system failures and improving the overall system performance.