Abstract: A multiprocessor system comprises a series of processors arranged to process data in an assembly-line fashion. Each processor includes an executor (execution unit, instruction decoder, and program counter) and a set of registers. Each set of registers is divided into two banks. At any given time, one bank is the “active” bank that is accessible by the local processor, and the other is the “shadow” bank, inaccessible to the local processor. Each processor but the last writes in parallel to its active bank and to the shadow bank of the immediate downstream processor. When all processors have completed working the data in their respective possession, a context-switch is performed switching register banks so that former active banks become shadow banks and former shadow banks become active banks. This makes data that was being processed by an upstream processor virtually immediately available to a local processor.

Abstract: A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of a immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. If a sequential read operation is indicated, the same-set can also be accessed to the exclusion of the other sets provided the requested address does not correspond to the beginning of a line address. (In that case, the sequential read crosses a cache-line boundary.

Abstract: A data-cascading hierarchically arranged electrically configurable logic device (ECD) system and an enable-cascading hierarchically arranged ECD system are provided. In both cases, the configuration bitstream includes a local count and at least one remainder count for each ECD. The local count determines the amount of configuration data to be stored locally. By setting this count to zero, an ECD can be bypassed. The remainder count determines the amount of data to be stored by devices down one hierarchical branch from the local ECD. By setting this count to zero, this branch can be bypassed and ECDs of a second branch can be configured sooner. In the data cascading system, the counts determine how data is routed through the ECDs. In the enable cascading system, the data is broadcast to all ECDs. The counts determine when and if the configuration enable inputs of downstream ECDs are to be activated.

Abstract: A thermal reactor for epitaxial deposition on a wafer comprises a double-dome vessel and dual heat sources. Each heat source comprises inner and outer circular arrays of infrared lamps. Circumferential heating uniformity is assured by the cylindrical symmetry of the vessel and the heating sources. Radial heating uniformity is provided by independent control of inner and outer heating arrays for both the top and bottom heat sources. The relative temperatures of wafer and susceptor are controlled by adjusting relative energies provided by the upper and lower heat sources so that backside migration. Reduced pressure operation is provided for by the convex top and bottom domes. Due to the provided control over transmitted energy distribution, a susceptor can have low thermal mass so that elevated temperature can be achieved more quickly and cooling can be facilitated as well. This improves throughput and reduces manufacturing costs per wafer. Reagent gas introduction can be axial or radial as desired.

Abstract: An improved semiconductor wafer transfer method and system incorporates a combination of wafer retractor (14) and wafer lifters (16) built into each processing chamber with a modified transport arm (12) to achieve large enhancements in wafer exchange speeds. The transport arm (12) brings a new wafer into a processing chamber (18) where an already processed wafer waits for retrieval, having been lifted into the central portion of the chamber by lifters (16). In a simultaneous action, lifters (16) lower the processed wafer onto a lower platform of the transport arm (12) while the wafer retractor (14) removes the new wafer from an upper platform of the transport arm (12). Once the transport arm (12) removes the processed wafer from the chamber (18), the retractor (14) lowers the new wafer onto the wafer lifters (16) and processing begins.

Abstract: An epitaxial reactor system provides for enhanced gas flow control and, thus, deposition uniformity. Gross reactant gas flow is set by a main flow controller which delivers unequal amounts to a reaction chamber via two nozzle assemblies. A supplemental flow controlled by an auxiliary flow controller is used to balance the flow rates through the nozzle assemblies so as to reduce spiralling of the gas flow within the chamber. Vertical ridges on a shroud within the reaction chamber help guide incoming gases vertically, further minimizing spiralling. The direction of gas flow from each nozzle assembly is controlled by two actuators, one controlling orientation along a coarse diagonal to obtain an overall vertical uniformity of deposition; the other actuator controls orientation along a fine diagonal to balance inter- and intra-wafer deposition uniformity. This arrangement optimizes the convenience in attaining vertical uniformity.

Abstract: A thermal reactor system for semiconductor processing incorporates a reaction vessel with a rectangular quartz tube with reinforcing parallel quartz gussets. The gussets enable sub-ambient pressure processing, while the rectangular tube maximizes reactant gas flow uniformity over a wafer being processed. The gussets facilitate effective cooling, while minimally impairing heating of the wafer by allowing minimal wall thickness. The thermal reactor system further includes a gas source for supplying reactant gas and an exhaust handling system for removing spent gases from and establishing a reduced pressure within the reaction vessel. An array of infrared lamps is used to radiate energy through the quartz tube; the lamps are arranged in a staggered relation relative to the quartz gussets to minimize shadowing. In addition, other non-cylindrical gusseted vessel geometries are disclosed which provide for improved sub-ambient pressure thermal processing of semiconductor wafers.