Abstract: Disclosed is a system using a SAS host controller and SAS expanders to control multiple SATA end devices where the memory contained on the SAS host controller is fixed to ease the cost and power consumption of the SAS host controller device, but where there is an expanded ability to support additional SATA end devices by configuring the allowed native command queue depth to be smaller for each SATA end device, thus allowing more SATA end devices to be supported by a single SAS host controller. An embodiment of the invention has three possible preset configuration states: thirty-two SATA end devices with a native command queue depth of thirty-two; sixty-four SATA end devices with a native command queue depth of sixteen; and one-hundred-twenty-eight SATA end devices with a native command queue depth of eight.

Abstract: Disclosed is an object oriented netlist database that stores electrical circuit data parsed from a netlist text file that is formatted in HSPICE or Circuit Design Language (CDL) formats. To obtain the netlist text file, an electrical circuit schematic of an electrical circuit is created using a commercially available electrical schematic capture software tool. The electrical schematic capture software tool is then directed to create the netlist text file that is representative of the electrical circuit. A netlist text file parser program first creates the object oriented netlist database structure, then parses the netlist text file, and finally fills the netlist database with objects that represent the electrical circuit data contained in the netlist text file. Analysis software may be written to programmatically access the electrical data stored in the netlist database using netlist database access subroutines that are part of the netlist database objects.

Abstract: Disclosed is a method for automatically testing the deskew setting for the clock in a parallel data interface. The deskew value is varied to a high and a low limit to the point where errors occur when transmissions occur. After determining the high and low operable limits of the deskew values, an optimum deskew setting may be determined and set for the system. The present invention may be used as a design verification technique, for optimizing a system after integration, or for further optimization of the deskew value after performing a training pattern for optimizing transmission performance.

Abstract: An amplifier for a differential signal drain is able to amplify a signal over a frequency range and boost the signal within a specified frequency range. A resistor is placed between the drain and gate of the first transistor of a cascode amplifier and can be selected to provide additional signal boost at a specified input frequency. An additional input transistor may be added to provide a stepped amplification over the frequency range. The amplifier is further able to reject common mode signals by using regulating transistors.

Abstract: Static timing analysis results from multiple corner cases are combined to create a differential results table that may be used to identify components that are a high risk for failure. These results may be combined with a schematic analysis tool that finds overlapping logic cones for specific nodes of a circuit such as a failing output pin. These tools are specifically adapted to assist an engineer in the design and debugging of complex circuits, such as integrated circuits.

Abstract: A current amplifier has a variable resistor or capacitor to provide a high frequency boost. Additionally, additional transistors may be switched in and out of the circuit to provide different gains at lower frequency. The combination of variable resistors or capacitors and the switchable transistors provides control over the low frequency gain of the amplifier and the transition region from low gain to higher gain.