Abstract: Candidate architectures for an electronic design are created through a machine implemented method that includes initially generating one or more initial candidate architectures for the electronic design on a top abstraction level, and subsequently generating additional candidate architectures for the electronic design at one or more lower abstraction level, in accordance with periodic guidance provided by a designer. In one embodiment, the initial candidate architectures on the top abstraction level are generated in accordance with a behavioral specification of the electronic design, and an initial set of constraints on the electronic design, independently described, and include application of a de-abstraction transformation.

Abstract: Computer-implemented methods are described for, first, characterizing a specific category of information content—pornography, for example—and then accurately identifying instances of that category of content within a real-time media stream, such as a web page, e-mail or other digital dataset. This content-recognition technology enables a new class of highly scalable applications to manage such content, including filtering, classifying, prioritizing, tracking, etc. An illustrative application of the invention is a software product for use in conjunction with web-browser client software for screening access to web pages that contain pornography or other potentially harmful or offensive content.

Abstract: A linear time display including a first and a second time clock for a first and a second locale of a first and a second time zone is disclosed. In one embodiment, each linear time clock includes a plurality of time unit representations. A first visual indicator is displayed to correlate a first time unit representation in the first linear clock to a corresponding time unit representation in the second linear clock, and a second visual indicator is displayed to correlate a second time unit representation in the second linear clock to a corresponding time unit representation in the first linear clock. A time difference represented by the spatial difference between the first and second visual indicators is also displayed.

Abstract: Methods of instrumenting synthesizable source code to enable debugging support akin to high-level language programming environments for gate-level simulation are provided. One method of facilitating gate level simulation includes generating cross-reference instrumentation data including instrumentation logic indicative of an execution status of at least one synthesizable register transfer level (RTL) source code statement. A gate-level netlist is synthesized from the source code. Evaluation of the instrumentation logic during simulation of the gate-level netlist facilitates simulation by indicating the execution status of a corresponding source code statement. One method results in a modified gatelevel netlist to generate instrumentation signals corresponding to synthesizable statements within the source code. This may be accomplished by modifying the source code or by generating the modified gate-level netlist as if the source code was modified during synthesis.

Abstract: A data extraction tool is provided to extract filtered connectivity and geometrical data for specified layout cell hierarchies of an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The connectivity and geometrical data for each layout cell hierarchy are extracted at least in part in accordance with specified parasitic effect windows. In one embodiment, the data extraction tool includes a filtered extraction function that operates to extract connectivity and geometrical data for layout nets of each layout cell hierarchy of the IC design, one or more layout nets at a time. Additionally, one or more filtered databases are provided to store the filtered connectivity and geometrical data of the layout cell hierarchies.

Abstract: The present invention beneficially provides a method and apparatus that can support multiple HDLs in both the creation of new circuit designs and the use of legacy data such as IP blocks. Where a graphical design tool supports a first HDL and design data is provided in a second HDL, the present invention generates an interface description for the design data written in the first HDL, and then generates a graphical design unit based on the interface description. The resulting graphical design unit is supported by the graphical design tool.

Abstract: The present invention includes a net topology strategy, referred to as a J-tree model, that meets monotonicity and ring back constraints for nets with bi-directional drivers without much degradation in delay. The present invention includes a method that can be used to automatically construct a J-tree for a given net. A J-tree is generated by identifying at least two clusters of nodes and interconnecting the nodes so that each node has a sibling node that is the same distance from a parent node. Each cluster comprises at least a minimum geometric number of nodes. The nodes are interconnected by first locating a star point for each cluster so that the nodes in each cluster are equidistant from the star point. Then, the star point for each cluster is interconnected forming the topology.

Abstract: A linear time display including a first and a second time clock for a first and a second locale of a first and a second time zone is disclosed. In one embodiment, each linear time clock includes a plurality of time unit representations. A first visual indicator is displayed to correlate a first time unit representation in the first linear clock to a corresponding time unit representation in the second linear clock. In one embodiment, the linear time display is a digital device such as a digital watch, or a digital wireless phone. In another embodiment, the linear time display is an electro-mechanical time display, such as a wall mounted time display.

Abstract: An optimizing hardware-software co-verification system is disclosed including a number of bus interface models, a number of memory models, and a co-verification optimization manager for co-verifying a hardware-software system having memory. Co-verification is performed with a single coherent view of the memory of the hardware-software system, transparently maintained by the co-verification optimization manager for both the hardware and software verifications. This single coherent view includes at least one segment of the memory being viewed as configured for having selected portions of the segment to be statically or dynamically configured/reconfigured for either unoptimized or optimized accesses, wherein unoptimized accesses are performed through hardware verification, and optimized accesses are performed “directly” by the co-verification optimization manager, by-passing hardware verification.

Abstract: In accordance with a method and apparatus for synchronizing information browsing among multiple systems, a bridgeport system receives identifiers for data requests received in a first hardware system and automatically transmits the identifier of the requested data to one or more additional hardware systems. Each of these one or more additional hardware systems then retrieves the identified data, thereby keeping the data being provided in these hardware systems in synchronization.

Abstract: An improved method and apparatus for saturation detection in floating point to integer conversions is described. A floating point number is tested for saturation conditions based on an integer field size. From testing the saturation conditions on the floating point number, the present invention predicts whether a floating point number can be converted into an integer value having the given integer field size, or whether the integer field would be saturated. In one embodiment, the saturation conditions are tested on the floating point number in parallel with a floating point to integer conversion.

Abstract: A user centric approach to program product distribution, including a complementary multi-vendor source control system (MVSCS) suitable for use to practice the user centric distribution approach is disclosed. Under the user centric approach, versioning control information of the source files of various program products to be installed on various user computer systems are maintained on a user computer system by user computer system basis. Each user computer system or its proxy is provided with a portion or an entire MVSCS to facilitate receipt and storage into a common repository for the user computer system versioning control information of different source files of different software vendors, and to facilitate retrieval of selective versions of the different source files for the user computer system using versioning control information stored in the common repository for the user computer system.

Abstract: The present invention beneficially provides a method and apparatus for automatically removing acid traps from a hatched fill in a printed circuit board design. The printed circuit board design includes a cross-hatched fill area comprising boundary lines and cross-hatched lines within the boundary lines. Furthermore, the boundary lines and cross-hatched lines have a particular aperture. The printed circuit board design is automatically modified to fill partial hatch areas, if any, in the cross-hatched fill area. In one embodiment, the cross-hatched fill area is converted to a bit map of one dimensional edges representing the lines in the cross-hatched fill area. In this embodiment, partial hatch areas are identified based on the bit map, and edges are added in the identified partial hatch areas. Then, the embodiment converts the additional edges into corresponding lines in the printed circuit board design, wherein the lines have the particular aperture, to fill the partial hatch areas.

Abstract: Disclosed is a software distribution system using both differencing and compression techniques to distribute source files over a network while minimizing the network bandwidth needed to maintain and update a set of source files. In an embodiment, a sending computer maintains sets of source files in base and delta form. The delta source files contain difference information allowing a new version of a source file to be constructed, or reconstituted, from a previously reconstituted version. Prior to transmitting a source file in either base or delta form to a receiving computer, the sending computer compresses the source file using a dictionary-based compression scheme. The resulting tokenized source file is stored and then transmitted to the receiving computer along with versioning control information. The receiving computer stores the tokenized source file along with the versioning control information.

Abstract: An improved floating point unit (FPU), equipped to perform floating point to integer conversion and integer addition in addition to floating point addition, is described. In one embodiment, the FPU includes a shifter, a bypass datapath, and a bypass multiplexer. The shifter receives an operand input and a control input, and shifts the operand input in accordance with the control input. The bypass datapath bypasses the operand input around the shifter. The bypass multiplexer is coupled to the shifter and the bypass datapath. The bypass multiplexer selects the bypass datapath to enable an integer addition if the operand is an integer operand, and selects the shifter to enable a floating point addition or floating point to integer conversion if the operand is a floating point operand. In an alternate embodiment, the FPU includes an alignment unit, an arithmetic logic unit (ALU), a bypass datapath, and a bypass multiplexer. The alignment unit receives a first input and a second input, and aligns them.

Abstract: An apparatus for establishing a voice call to a PSTN extension for a networked client computer, and routing the voice call off of the network, is provided. In a first embodiment, the apparatus comprises a storage medium having stored therein a plurality of programming instructions coupled to an execution unit to execute the plurality of programming instructions to implement a set of communication services facilitating the establishment of the voice call to the PSTN extension. The set of communication services include services for receiving a request from the networked client computer requesting the voice call, determining the PSTN extension and controlling a computer telephony interface to route the voice call from the packet switched network to the PSTN extension.