Abstract: A process of preparing a product gas mixture comprising CO and H2 from a light hydrocarbon and O2 mixture is disclosed. The process includes contacting a reactant gas mixture comprising a C1-C5 hydrocarbon and a source of molecular oxygen with a catalytically effective amount of a supported catalyst comprising nickel and rhodium. The catalyst and reactant gas mixture is maintained at catalytic partial oxidation promoting conditions of temperature and pressure during the contacting period, which is preferably 10 milliseconds or less. Certain preferred catalysts comprise an alloy of about 10-50 weight percent nickel and about 0.01-10 weight percent rhodium on a porous refractory support structure.

Abstract: For bypassing a computer system coupled between first and second network links, the computer system executes a software which provides a predetermined control signal on a control line. The control line is polled by a bypass device that will cause the computer system to be bypassed when said control signal is not present on the control line. The control signal may be in the form of periodic pulses and a bypassing is caused when a pulse is not received on the control line within a predetermined period of time.

Abstract: An apparatus and method for executing floating-point store instructions in a microprocessor is provided. If store data of a floating-point store instruction corresponds to a tiny number and an underflow exception is masked, then a trap routine can be executed to generate corrected store data and complete the store operation. In response to detecting that store data corresponds to a tiny number and the underflow exception is masked, the store data, store address information, and opcode information can be stored prior to initiating the trap routine. The trap routine can be configured to access the store data, store address information, and opcode information. The trap routine can be configured to generate corrected store data and complete the store operation using the store data, store address information, and opcode information.

Abstract: A computer is provided having a SCSI subsystem and multiple SCSI devices connected to that subsystem. Those devices involve electromechanical motors which require a greater amount of current during times needed to spin-up the motor-driven devices to a steady-state velocity than current needed to maintain that velocity. Each SCSI device includes an inquiry page indicating attributes of that device and whether that device supports fast spin-up. If a device supports fast spin-up, firmware within the computer is activated during ROM POST operations forwards a command to begin a spin-up operation on one SCSI device before the prior device has completed its spin-up operation. In this manner devices which support fast spin-up can concurrently spin-up to their constant velocity value so as to minimize the initialization process of the computer system subsequent to reset or boot-up of the system.

Abstract: A software methodology to control replacement of one or more selected pages within a cache memory in a computer system. The operating system designates one or more pages containing critical data, text or other digital information as hot pages within a physical system memory in the computer system and prevents replacement during execution of various application programs of these hot pages when cached. The operating system inhibits allocation of the conflict pages that would map to cache locations occupied by a cached hot page, thereby preserving the hot page within the cache memory. The conflict pages are placed at the bottom of a free list created in the system memory by the operating system. The operating system scans the free list using a pointer while allocating free system memory space at run-time. The system memory pages are allocated from the free list until the pointer reaches a conflict page.

Abstract: A method, apparatus and system for treating a stream containing H2S are disclosed. A preferred method comprises mixing the stream containing H2S with a light hydrocarbon stream and an oxygen containing stream to form a feed stream; contacting the feed stream with a catalyst while simultaneously raising the temperature of the stream sufficiently to allow partial oxidation of the H2S and partial oxidation of the light hydrocarbon to produce a product stream containing elemental sulfur, H2O, CO and hydrogen, and cooling the product stream sufficiently to condense at least a portion of the elemental sulfur and produce a tail gas containing CO, H2, H2O and any residual elemental sulfur, and any incidental SO2, COS, and CS2 from the hydrocarbon stream or produced in the process. The tail gate is contacted with a hydrogenation catalyst so that CO is then reacted with water to produce CO2 and hydrogen and any elemental sulfur, SO2, COS, and CS2 in the tail gas is preferably converted into H2S.

Abstract: A clock divider circuit having a fifty per cent duty cycle and multiple integer ratios for dividing an input clock signal. In one embodiment, a clock divider circuit may include a chain of serially-coupled flip-flops. The chain may include at least a first and a second flip-flop, both of which may be triggered by a first edge of an input clock signal. A third flip-flop, coupled to (but not part of) the chain may be configured to be triggered by a second edge of the input clock signal. The third flip-flop may be coupled to an output circuit. In addition to receiving the output signal from the third flip-flop, the output circuit may also receive signals from the chain of serially-coupled flip-flops. The output circuit may drive a second clock signal, which may be produced by dividing the first clock signal based upon the signals it receives. The first clock signal may be divided by an even or an odd integer ratio, or may be divided by an integer ratio (e.g. 2.

Abstract: A video decoder is provided with robust error handling and concealment. In one embodiment, the video decoder detects syntactic, semantic, and coding errors in encoded slices of macroblocks. An error handler determines the number of remaining un-decoded macroblocks in the corrupted slice and replaces these corrupted macroblocks using substitute DCT coefficient matrices and motion vectors. The zero-frequency DCT coefficient of each substitute matrix is set equal to the zero-frequency DCT coefficient of the last uncorrupted macroblock, while the higher frequency DCT coefficients are set equal to zero. The substitute motion vectors are provided from a concealment vector memory which buffers the motion vectors of the previous macroblock row. In this way, intelligent approximations are made for the missing macroblocks, effectively masking the video bitstream error.

Abstract: An isochronous bus may includes a data signal, a data valid signal, a frame synch signal and a clock signal. The bandwidth of the data signal is partitioned into a plurality of frames. The frame rate may be selected based upon the sample rate of one of the isochronous devices connected to the isochronous bus or maybe some divisor of the data rate of the isochronous bus. Each frame is partitioned into a plurality of data channels. Each data channel transmits data from an isochronous device. A number of bit time slots are allocated to each data channel. The number of bit time slots allocated to each data channel varies based upon the sample rate of the device corresponding to the data channel. In one embodiment, each data channel is allocated more bit time slots than the nominal samples of its corresponding device. In this manner, any drift of the sample clock may be accommodated. A data valid signal is transmitted synchronous to the data signal and the clock signal.

Abstract: A process and catalyst are disclosed for the catalytic partial oxidation of light hydrocarbons to produce synthesis gas. The process involves contacting a feed stream comprising the hydrocarbon feedstock and an oxygen-containing gas with a catalyst in a reaction zone maintained at conversion-promoting conditions effective to produce an effluent stream comprising carbon monoxide and hydrogen in a molar ratio of about 2:1 H2:CO. A preferred supported catalyst used in the process includes nickel and magnesium oxide, with a promoter selected from the group including manganese, molybdenum, tungsten, tin, rhenium, bismuth, indium, phosphorus, and combinations thereof.

Abstract: A printed circuit board assembly with improved bypass decoupling for BGA packages. In one embodiment, a capacitor may be interposed between a BGA package and a PCB within a perimeter of the contact pads that form a BGA footprint. The capacitor may have physical dimensions which allow a BGA package to be mounted such that there is no physical contact between the capacitor and the BGA.

Abstract: A microprocessor configured to decode a plurality of instruction bytes in parallel is disclosed. The microprocessor may comprise a plurality of single-byte decoder/execution units that are configured to receive instruction bytes and cross-talk to determine instruction boundaries and instruction field boundaries. Once and instruction has been identified, a determination is made as to whether or not the instruction is a simple instruction. Simple instructions are executed within the decoder/execution units, while complex instructions are forwarded to full-fledged functional units. A computer system and method for predecoding instructions are also disclosed.

Abstract: A system and method for controlling an instrumentation system, wherein the present invention includes an improved instrument driver software architecture. The instrument driver software architecture of the present invention provides a number of features, including instrument interchangeability, i.e., the use of interchangeable virtual instruments or interchangeable instrument drivers, improved performance, an improved attribute model, improved range checking, and improved simulation features, among others.

Abstract: A built-in integrated connector module for a portable computer includes a support plate that attaches to a mini-PCI card and two communication jacks. Electronic interconnection such as a flex cable or wiring is provided between the jack and the mini-PCI card. The entire module is secured in supporting structures provided within the housing of a portable computer such that the module may be installed reliably and conveniently.

Abstract: A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating point unit is configured to schedule instructions older than the FLDCW-type instruction before the FLDCW-type instruction is scheduled. The FLDCW-type instruction acts as a barrier to prevent instructions occurring after the FLDCW-type instruction in program order from executing before the FLDCW-type instruction. Indicator bits may be used to simplify instruction scheduling, and copies of the floating point control word may be stored for instruction that have long execution cycles. A method and computer configured to rapidly execute FLDCW-type instructions in an out of program order context are also disclosed.

Abstract: The process comprises: etching, in a semiconductor substrate (2), at least one trench (3) with predetermined width and depth; depositing, on the substrate and in the trench, a stack of successive and alternate layers of Si1−xGex (0<x≦1) and Si (5-8), the number and the thickness of which depend on the final use intended for the heterostructure; and chemical-mechanical polishing in order to obtain a final heterostructure having a plane upper main surface, level with which the stack layers deposited in the trench are flush.

Abstract: Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node.

Abstract: In one embodiment, a multiprocessing computer system includes a plurality of nodes. The plurality of nodes may be interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote nodes memory. In the event of an error, an error status register of a system interface of the launching cluster node is set to indicate the occurrence of an error. The error may be the result of an access violation, or the result of a time-out occurrence in either the remote node or the initiating node. Various other errors may alternatively be reported. The system interface advantageously includes a plurality of error status registers, with a separate error status register provided for each processor included in the node. A process running on any of the processors of the node reads an error by issuing a transaction to a unique address, wherein the unique address is independent of the processor upon which the process is running.

Abstract: A test executive program which provides greatly improved configurability and modularity, thus simplifying the creation, modification and execution of test sequences. The test executive program includes process models for improved flexibility, modularity and configurability. Process models provide a modular and configurable entity for encapsulating operations and functionality associated with a class of test sequences. The process model thus encapsulates a “testing process” for a plurality of test sequences. The process model enables the user to write different test sequences without repeating standard testing operations in each sequence. The test executive program also includes step types for improved configurability. A step type is a modular, identifiable unit configured by the user which defines common properties and/or operations associated with a plurality of steps.

Abstract: A system is disclosed for synchronizing a clock in a well containing a drill string with a clock located near the surface of the well. The system includes devices for transmitting and receiving a pair of acoustic signals between locations associated with each clock and processing those signals. The system determines the time of arrival of each acoustic signal by analyzing the shape of a function of the acoustic signal chosen from a group of functions suitable to determine a clock offset with millisecond accuracy.