Abstract: A packet switch router that processes downstream digital information to provide dedicated bandwidth to each subscriber destination in a hybrid fiber coax (HFC) network. The router includes a network module that terminates a network connection, a switch that forwards data from the network module, and a channel module. The channel module includes a switch interface, a cell processing engine, one or more modulators, and a radio frequency (RF) transmitter network. The switch interface forwards packetized data from the switch to the cell processing engine. The cell processing engine organizes the packetized data into multiple data streams, encapsulates data in each data stream into data cells, and multiplexes the data cells into a multiplexed cell stream. Each modulator is configured to modulate a multiplexed cell stream into an analog signal. The RF transmitter network up converts and combines a plurality of analog signals into a combined electrical signal for transmission.

Abstract: Asynchronous sample rate conversion is performed using a noise-shaped numerically controlled oscillator (204,420) that generates a clock (207,428) that is synchronous to the system clock (217,424) but having a time average frequency that is equal to a multiple (X) of the asynchronous sample rate frequency required for the conversion. Unwanted spectral energy in the generated clock (207,428) is noise-shaped out of the pass-band and so does not degrade signal performance. For digital-to-analog conversion, the generated clock (207) is used to time an interpolation (206) of digital data (DATAFs) by an multiple X to produce an interpolated signal (DATAFsX) having a time average rate equal to the over-sampling frequency but being synchronized with the system clock (217). The interpolated signal (DATAFsX) is then converted (216) to an analog signal using a derivative of the system clock (217), or can be output as digital data at the rate derived from the system clock.

Abstract: Testing of a multi-module data processing system (20) includes performing a functional test on a module (42, 44, 46, 48, 50, 54) concurrently with an erase operation of a non-volatile memory module (34, 36). Because the erase operation requires multiple clock cycles to complete, and little or no interaction with a tester, a set of test patterns may be run on one or more of the modules (42, 44, 46, 48, 50, 54) while the erase operation is being performed. Between each test pattern, a special reset signal is provided to a reset unit (39) of a system integration unit (38). The special reset signal resets the modules (42, 44, 46, 48, 50, 54), without affecting the erase operation of the flash memory module (34, 36), in order to perform each test of the modules (42, 44, 46, 48, 50, 54) from a known state. Concurrent testing in this manner reduces the time required to test a multi-module data processing system.

Abstract: A CMOS implemented output buffer (10) provides ECL level output signals. The output buffer (10) is implemented in two stages. The first stage (36) includes an inverter having a resistor (39) in series with a P-channel transistor (38) and an N-channel transistor (40) and provides the initial buffering. The resistor (39) in the first inverter stage (36) is used to reduce a cross-over current in the second drive stage (42). The second stage (42) provides additional drive capability and includes an integral level converter. The integral level converter is implemented as a P-channel transistor (44) connected in series with the P-channel and N-channel output driver transistors (53 and 55). The P-channel transistor (44) provides the level shifting function to ECL levels for the second stage. The bias level of the P-channel transistor (44) determines the output logic swing.

Abstract: A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.

Abstract: An unbuffered flip-flop includes feedback control circuitry providing adaptive control of the internal node during the transfer and latching phases of the flip-flop to prevent back-writing. A complementary pair of transmission gates controlled by the output node are included in the feedback path between an output buffer and a feedback buffer. As noise voltage variations and spikes alter the voltage on the output node, the charge transmittance of the transmission gates is weakened or shut off, thereby preventing the incorrect logic state from being driven by the feedback buffer through to the input of the flip-flop's output buffer and causing back writing. Because the transmission gate transistors are complementary, one transistor or the other will be operating in a transmissive state for each of the bi-stable states of the output buffer during static operation of the flip-flop.

Abstract: A trailer microprocessor in a debugging tool runs code a known number of cycles behind a master and shadow pair of processors. A pipeline queues up bus activity from the shadow processor a number of cycles, and then outputs those signals to the trailer microprocessor to execute the same code and signals as the master and shadow microprocessors a known number of cycles behind. The outputs of the master and shadow microprocessors are compared and the trailer microprocessor is halted, along with the master and shadow, when a "mismatch" occurs between the outputs of the master and shadow processors. When the internal states of all three processors are scanned, the differences in the internal state of the shadow processor before and at a failure can be theoretically compared. The trailer microprocessor may be stepped cycle-by-cycle up to and past the point of failure of the shadow processor for further analysis.

Abstract: A cascaded integrator-comb (CIC) interpolation filter is included within a digital-to-analog converter (138) and includes two up-samplers (150, 164). The two up-samplers (150, 164) also include a sample-and-hold function. The first up-sampler (150) up-samples an output of a differentiator (140). The second up-sampler (164) up-samples an output of an integrator (152) This reduces the area and power requirements of the CIC interpolation filter, while providing approximately the same filtering performance in the pass band and transition band. The total over-sample ratio of the CIC interpolation filter is equal to the first up-sampling ratio multiplied by the second up-sampling ratio. The stop band requirements of the CIC interpolation filter determines the relative sizes of the first and second up-sampling ratios.

Abstract: A class A driver circuit (30) has an output stage with a plurality of selectable current sources (42). The selectable current sources (42) are used to optimize the drive capability of the output stage of the class A driver circuit (30) for different applications having different output impedance. In one embodiment, the selectable current sources (42) may be selectable, or switchable, using software programmed by a user. In another embodiment, the current sources may be automatically selected, based on sensing the output current provided to a resistive load. Also, in yet another embodiment, the selectable current sources (42) may be selectable based on the input signal of a first stage amplifier (32). A Miller compensation network (40) includes digitally controlled, switchable capacitors (129) and resistors (128), and provides the necessary amount of Miller compensation for the selected current sources.

Abstract: A multiplexed output circuit (200) for use in an integrated circuit (500) such as a static random access memory locates a plurality of amplifiers (206, 208), a plurality of output buffers (210, 212), and an output driver (201) on the integrated circuit (500), such that the routing parasitic delay between the plurality of output buffers and the output driver (218-224) is greater than the routing parasitic delay between any output buffer (e.g. 212) and its corresponding amplifier (e.g. 206).

Abstract: An instruction fetch and issuance unit (200) fetches two instruction words and issues at least one instruction word to an instruction decoder (250) per clock cycle. Two multiplexers (220, 230) receive the two fetched instructions and one or both of two of three words stored in an instruction register (240). A controller (210) selectively controls (207-209), in accordance with a state diagram (300), the loading of three words into the instruction register (240) from among the inputs of the multiplexers (220,230). The instruction register (240) issues up to two instructions per clock cycle without requiring the processor to stall to retrieve an additional word, allowing efficient issuance of a double-word instruction or two instructions in parallel.

Abstract: Circuitry is implemented within an integrated circuit ("chip") (101) which is an IEEE 1149.1 compliant device capable of performing JTAG testing (104), such as an EXTEST or CLAMP testing procedure. Upon exiting of either of these procedures, the input/output pins (210) of the chip are placed in a known state, which may be a high impedance state.

Abstract: A method and circuit for optimally controlling memory array bit line precharge timing to increase memory frequency of operation by generating a precharge output (110) for memory array bit lines in response to the earliest asserted control input among precharge control inputs. A write precharge signal (218) early enables a write precharge operation by enabling the precharge signal (110) a delayed period after an enabling falling dock edge of clock (104), as indicated by a write precharge enable signal (210), and during a write cycle, as indicated by a write precharge trigger (212). Thereafter, a default precharge trigger (216) is enabled to ensure that write precharging operation continues for an extended and optimal duration. A read precharge trigger (214) enables precharging after a read operation by enabling the precharge signal (110) in close proximity to the disabling of read sense amplifiers within the memory array to enhance post-read precharging.

Abstract: After a portion of a cache line has been zone written from a processor core (102) to a cache array (105), a read access received from the processor core (102) for one or more bytes within the cache line corresponding to the zone written data can be satisfied before a cache fill operation initiated by the zone written operation is completed. If the read access is for one or more bytes of the cache line which was not previously zone written, then the requested data is passed directly from the filling bus (113) to the processor core (102) as soon as it becomes valid on the filling bus (113). If the read access is for one or more bytes of the zone written data, then those one or more bytes are read from the cache array (105) to the processor core (102) regardless of the progress of the cache fill. All read accesses to filling cache lines are serviced in the minimum amount of time by satisfying the access immediately upon availability of only the exact portion requested.

Abstract: A pulse width modulator (PWM) system (100) detects several load current conditions to completely correct for the distortion caused by deadtime insertion when driving an inverter-fed inductive load, such as a three-phase AC motor. The system includes an inexpensive voltage sensor (140) which senses the output voltage at the end of each successive dead time interval in which neither a pullup transistor (51) nor a pulldown transistor (52) is driving. The system (100) includes a programmable PWM (125), two storage elements (131,132) such as D-type flip flops, and a memory-mapped register (133). The register stores the output of the flip-flops to indicate a near-zero load current condition. When it detects this condition, the system (100) changes the duty cycle of the PWM output signals to yield output voltages and currents which more closely approximate a sine wave. The system (100) is particularly useful as part of a low-cost microcontroller (120).

Abstract: Accurate delay testing of integrated circuits containing memory arrays embedded in combinational logic utilizes actual memory array timing. Actual memory timing signals provide the timing for bypassing the memory in SCAN Mode. The result is that simulated memory accesses during SCAN Mode testing have the same timing as actual memory accesses have during functional mode operation. Thus delay testing during SCAN Mode through paths containing both combinational logic and memory arrays accurately determines path delays.

Abstract: An input stage (200) for use in a Sigma-Delta analog-to-digital converter (300) that utilizes a frequency independent impedance (202) in parallel with a frequency dependent impedance (210, 212). An analog input signal (Vin) is concurrently passed through both impedances to a terminal of an operational amplifier (208). A feedback reference (REF) from the A/D converter (316) is also coupled to the terminal of the op amp (208) via a second frequency independent impedance (204). The frequency dependent impedance (210, 212) enables amplification of the input signal at higher frequencies to boost signal-to-noise ratio at such frequencies. Thus, the frequency dependent impedance significantly improves signal-to-noise ratio in the Sigma-Delta converter, thereby avoiding any pre-filtering of the Sigma-Delta inputs.

Abstract: A data processing system (10) flexibly interfaces with both a variety of memory devices and external peripheral devices. A control register (94) is provided for dynamically controlling a timing relationship for read and write accesses executed by the system. A first set of bits (PA) in the control register provides timing control for an initial amount of time required to read a first data value from an external device. A second set of bits (SA) in the control register provides timing control for each successive amount of time required to read a successive data value from the external device.

Abstract: An output driver (10) for a bus interface and associated method of operation. The output driver (10) comprises a first driver circuit (12), a second driver circuit (14), and a controller (16). The first driver circuit (12) provides data at a first current level to an output (18) while the second driver circuit (14) provides data to the output (18) at a second current level when activated. The controller (16), by selectively operating the first driver circuit (12) and the second driver circuit (14) causes the output driver (10) to selectively operate in differing modes of operation over time. In this fashion, the output driver (10) operates in Classical Mode (84), Active Negate Mode (80), Pulsed Negation Mode (82), and Differential Mode (86) based upon the requirements of peripheral devices (106, 108. 110. 112) and peripheral bus (20) requirements.

Abstract: In a portable electronic device, a method and apparatus for providing a predetermined portion of a limited resource from a programmable resource allocators (PRAs) (240) to a processor (22) to execute a task (210) optimally. The processor (22) programming the PRA with a resource utilization input (RUI) (250) prior to executing the task (210). The RUI (250) stored in a task descriptor (220), and the task descriptor (220) and the task (210) stored in the memory (200).