Patents Represented by Attorney, Agent or Law Firm Crawford PLLC
  • Patent number: 6546524
    Abstract: A component-based method and system for structured use of a plurality of software tools. In various embodiments, components are used to package objects that are constructed to test an electronic circuit design using different software tools. Flow files describe different execution sequences for selected ones of the plurality of software tools, and a first set of objects contains one or more methods for interfacing with a selected one or more of the flow files. A second set of objects contains one or more methods for collecting data from the software tools and entering the data in a database. The components include one or more methods that invoke one or more methods of the first and second sets of objects.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: April 8, 2003
    Assignee: Xilinx, Inc.
    Inventors: Ajay S. Chankramath, Eamonn G. Ryan
  • Patent number: 6528356
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: March 4, 2003
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Patent number: 6524189
    Abstract: A multi-player game system using a mobile telephone and a game unit is disclosed. The present invention links multiple users having game units with mobile phones using a low power radio link. The present invention includes at least one mobile phone having a first transceiver for providing connections to a cellular network and a second transceiver for providing short-haul connectivity, and a plurality of game units for interfacing with a plurality of players, each of the game units having a third transceiver for providing short-haul connectivity, wherein the mobile phones and the game units are linked by the second and third transceivers therein to enable a game to be played on the game units by the plurality of players. In at least one of the mobile phones, the second transceiver is a short range wireless transceiver. At least one mobile phone is used to download a game to the game units and the game units include a group selection interface for choosing players to include in a gaming group.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: February 25, 2003
    Assignee: Nokia Corporation
    Inventor: Heikki Rautila
  • Patent number: 6511068
    Abstract: A system, method and program for playing multiple, communal-card poker games simultaneously. A plurality of selectable starting hands of cards are presented to a participant. Each of the selectable starting hands represents a potential subset of a resulting poker hand, and does not of itself represent a playable hand. The participant selects one of the starting hands for use in all of the concurrently-played poker games. A plurality of communal-card flops are presented to the participant. The number of communal-card flops displayed corresponds to the number of poker games to be concurrently-played. A plurality of participant resulting poker hands are derived, one for each combination of the participant's selected starting hand and the plurality of communal-card flops. A plurality of remaining resulting poker hands are also derived, one for each combination of non-selected starting hands and each of the communal-card flops.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: January 28, 2003
    Assignee: Sklansky LLC
    Inventors: David Bruce Sklansky, Bradley Berman
  • Patent number: 6510547
    Abstract: Method and apparatus for evolving an object using simulated annealing and genetic processing techniques. In various embodiments, simulated annealing and genetic processing techniques are combined to evolve a computer-represented object. In each iteration an object is mutated in proportion to a mutation level, and the mutated object is evaluated relative to satisfaction of predetermined criteria. The mutation level is reduced with each iteration as the object approaches a final solution. Poorer-performing objects are selectively mutated or discarded based on a probabilistic function. As the object approaches a final solution, the probability of keeping and mutating poorer-performing objects is reduced.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: January 21, 2003
    Assignee: Xilinx, Inc.
    Inventor: Delon Levi
  • Patent number: 6491115
    Abstract: A system, apparatus and method for automatically limiting the thrust force applied to a drill string during an underground boring process, in order to prevent the deformation or collapse to the drill rods due to reaching the yield point of the rods. One or more drill string characteristics that have an impact on the yield point of the drill string, or portions of the drill string, are determined. The yield point of the drill string or portion is computed, where the yield point is computed as a function of the drill string characteristics. The thrust force imparted to the drill string is adjusted in response to the computed yield point.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: December 10, 2002
    Assignee: Vermeer Manufacturing Company
    Inventors: Mark Van Houwelingen, Randy Runquist, Brian J. Bischel, Mark R. Stelter, Gregg A. Austin
  • Patent number: 6484818
    Abstract: A system and method for controlling an underground boring tool involves the use of one or more of a gyroscope, accelerometer, and magnetometer sensor provided in or proximate the boring tool. The location of the boring tool is detected substantially in real-time. A controller produces a control signal substantially in real-time in response to the detected boring tool location and sensed parameters of a boring tool driving apparatus. The control signal is applied to the driving apparatus to control one or both of a rate and a direction of boring tool movement along the underground path. The gyroscope, accelerometer, and magnetometers may be of a conventional design, but are preferably of a solid-state design. Telemetry data is communicated electromagnetically, optically or capacitively between the navigation sensors at the boring tool and the controller via the drill string or an above-ground tracker unit.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: November 26, 2002
    Assignee: Vermeer Manufacturing Company
    Inventors: Kevin L. Alft, Gregory W. Draper, Hans Kelpe
  • Patent number: 6435286
    Abstract: An apparatus and method for determining a location and an orientation of an underground boring tool by employment of a radar-like probe and detection technique. The boring tool is provided with a device which generates a specific signature signal in response to a probe signal transmitted from above the ground. Cooperation between the probe signal transmitter at ground level and the signature signal generating device provided at the underground boring tool results in accurate detection of the boring tool location and, if desired, orientation, despite the presence of a large background signal. Precision detection of the boring tool location and orientation enables the operator to accurately locate the boring tool during operation and, if provided with a directional capacity, avoid buried obstacles such as utilities and other hazards. The signature signal produced by the boring tool may be generated either passively or actively, and may be a microwave or an acoustic signal.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: August 20, 2002
    Assignee: Vermeer Manufacturing Company, Inc.
    Inventors: Gregory S Stump, Christopher T. Allen
  • Patent number: 6404776
    Abstract: A multimedia communication arrangement processes and multiplexes different types of data, including data from an adaptive data rate data source and a nonadaptive data rate data source, to substantially increase data throughput over a communication channel. The rate at which data is collected from the adaptive data rate data source varies based on the available channel bandwidth of the modem. The transmission rate is optionally adjusted in response to a detected error rate. Furthermore, the amount of filtering performed by a video camera on an image before the image is encoded by a codec can be adjusted. In addition, a data recovery terminal optionally selectively adjusts intervals at which received audio data is sampled to potentially reduce latency periods.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: June 11, 2002
    Assignee: 8 × 8, Inc.
    Inventors: Paul Augustin Voois, Barry Dean Andrews, Truman Joe, Philip Stanley Bednarz
  • Patent number: 6347395
    Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: February 12, 2002
    Assignee: Koninklijke Philips Electronics N.V. (KPENV)
    Inventors: Robert Payne, Mark Bapst, Timothy Pontius
  • Patent number: 6309804
    Abstract: A semiconductor device is manufactured using an acid treatment process to eliminate the adverse effects of contamination, such as amine-airborne contamination. Consistent with one embodiment of the present invention, the semiconductor device is formed by applying a DUV-type photoresist over the wafer surface, exposing the photoresist to DUV light, treating the exposed photoresist with an acid vapor, and thereafter baking the exposed wafer.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: October 30, 2001
    Assignee: Philips Semiconductor, Inc.
    Inventors: David Ziger, Christopher Robinett
  • Patent number: 6304988
    Abstract: A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, a predetermined command transmitted over the bus causes the scan test ports to be coupled to the bus and the input/output ports to be decoupled from the bus. Test data may then be transmitted to and from the logic circuits via the bus. When testing is complete, a second predetermined command transmitted over the bus causes the scan test ports to be decoupled from the bus and the input/output ports to be coupled to the bus.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: October 16, 2001
    Assignee: Philips Semiconductors, Inc.
    Inventor: Paul S. Levy
  • Patent number: 6301008
    Abstract: A semiconductor fabrication process permits for narrowing linewidths using Optical End of Line Metrology (OELM). OELM involves measuring relative line shortening effects that are inherent in many semiconductor fabrication processes using optical overlay instruments. According to one embodiment, the process involves a frame that has two adjacent sides which are constructed of lines and spaces. The frame is imaged onto a wafer, but the optical line measurements used to implement the frame over-predict actual shortening of the lines.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: October 9, 2001
    Assignee: Philips Semiconductor, Inc.
    Inventors: David Ziger, Pierre Leroux
  • Patent number: 6282272
    Abstract: The present invention provides a method and interface for browsing the internet using a telephone circuit having keys for generating DTMF codes. The interface includes a memory and a processor and is coupled to the telephone circuit and display. The interface receives a first DTMF code requesting access to the internet and, in response to the first DTMF code, loads a Web browser in its memory. The interface then receives a second DTMF code from the telephone circuit and converts the second DTMF code into a Web browser command using an interpretation protocol. The Web browser command is then executed using the interface, thereby enabling a user to access the internet via manual operation of the keys of the telephone is circuit.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: August 28, 2001
    Assignee: Netergy Networks, Inc.
    Inventors: Michael Noonen, Kevin Deierling, Keith Barraclough, Bryan R. Martin, Yuenwah Sing, Joseph L. Parkinson
  • Patent number: 6252239
    Abstract: The present invention is directed to semiconductor chip analysis involving evaluation of a thickness of material in the chip, for example, as the chip is being thinned. According to an example embodiment of the present invention, a semiconductor die having a buried insulator (BIN) layer between a circuit side that is opposite a back side is analyzed. Light is directed at a selected area at the back side that is over a portion of material that has been reduced in thickness relative to the thickness of an unaltered die. The light has sufficient intensity to pass through the BIN layer and sufficient photon energy to cause the generation of electron-hole pairs in the die on the side of the BIN layer opposite the back side of the die. The electron-hole pairs generate an electrical output from the semiconductor die that is monitored and used to evaluate the thickness of the material.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: June 26, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rama R. Goruganthu, Richard Blish, II
  • Patent number: 6248600
    Abstract: Post-manufacturing analysis of a semiconductor device is enhanced via a method that uses a light emitting diode (LED) formed in a semiconductor die. According to an example embodiment of the present invention, a LED is formed within a semiconductor die having a circuit side opposite a back side. The LED is activated and generates radiation. Substrate is removed from the device, and the amount of radiation that passes through the substrate is detected. The amount of radiation that passes through the die is a function of the absorption characteristics of the die and the substrate thickness. By detecting the radiation and using the absorption characteristics of the die, the amount of substrate remaining in the back side of the die is determined and the substrate removal process is controlled therefrom.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: June 19, 2001
    Assignee: Advanced Micro Devices
    Inventors: Michael R. Bruce, Jeffrey D. Birdsley, Rosalinda M. Ring, Rama R. Goruganthu, Brennan V. Davis
  • Patent number: 6248603
    Abstract: Semiconductor structures having dielectric material layers that are below 3 nanometers in thickness can now be measured with greater precision and in less time using a SIMS device. In an example embodiment of the present invention, a method of measuring the thickness of a dielectric material layer of a semiconductor structure formed on a substrate includes directing a high energy ion beam at a portion of the substrate and sputtering off a plurality of targeted ions from the substrate. The thickness of the dielectric material layer is then determined as a function of a dosage level of the targeted ion and a density of the targeted ion in the dielectric material.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: June 19, 2001
    Assignee: Advanced Micro Devices
    Inventors: Clive Martin Jones, Jin Zhao
  • Patent number: 6230069
    Abstract: A system and method for controlling the manufacture of semiconductor wafers using model predictive control is provided. In accordance with one embodiment, a tool output of the manufacturing tool is determined based on a first wafer run. Using the tool output, a tool input for a subsequent wafer run is determined by minimizing an optimization equation being dependent upon a model which relates tool output to tool process state and tool process state to tool input and previous tool process state. The tool input is then provided to the manufacturing tool for processing a second wafer run. In this manner, processing by the tool or tool age is taken into account in determining the tool input for a subsequent run. This can reduce variations in tool output from run-to-run and improve the characteristics of the ultimately formed semiconductor devices.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: May 8, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William Jarrett Campbell, James Anthony Mullins, Anthony John Toprac
  • Patent number: 6229161
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: May 8, 2001
    Assignee: Stanford University
    Inventors: Farid Nemati, James D. Plummer
  • Patent number: 6225923
    Abstract: The encoder arrangement and bit-exact IDCT protocol provides methods and arrangements that prevent an accumulation of errors between a transmitting codec and a receiving codec. One example embodiment is directed to an arrangement for use in a first terminal for communicating representations of images with a second terminal using a communications channel on which communication has been established between the first terminal and the second terminal. The arrangement includes a processor-based decoder/encoder circuit and a bit-exact circuit. The processor-based decoder/encoder circuit is arranged to process video data using an inverse transformer loop. The bit-exact circuit prevents unacceptable accumulation of an error within the inverse transformer loop by using the inverse transformer in the loop according to a bit-exact specification between the encoder and decoder in the respective first and second terminals.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: May 1, 2001
    Assignee: Netergy Networks, Inc.
    Inventor: D. Barry Andrews