Patents Represented by Attorney Crowell & Morin LLP

Find this attorney in the Justia Lawyer Directory

  • Semiconductor device and fabrication method therefor
    Patent number: 6949829
    Abstract: With a stopper layer 19 as an etching stopper, a second groove 14a and a contact hole 13a are formed. Copper is buried inside the second groove 14a and the contact hole 13a, thereby forming a plug layer 22 and an overlying wiring layer 21 connected to an underlying wiring layer 17 via the plug layer 22. The stopper layer 19 is comprised of Si, C and N as essential components. First and second cap layers 18 and 23 are also comprised of Si, C and N as essential components.
    Type: Grant
    Filed: September 11, 2001
    Date of Patent: September 27, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Akahori, Gishi Chung, Kohei Kawamura