Abstract: An input protection circuit for a semiconductor memory device senses when the level of an external input signal drops below a reference voltage corresponding to a predetermined logic level, thereby enabling instant correction. The input protection circuit is interposed between an external power voltage terminal and an input terminal of the input buffer, and the external power voltage is transferred to the input terminal of the input buffer when the level of the external input signal applied to the input terminal drops below the predetermined logic level. The circuit includes an internal reference voltage generator which supplies a voltage having a level corresponding to the predetermined logic level and designed to compensate for a known device offset so that the external input signal applied to the input terminal can be instantly corrected.