Abstract: A computer is power managed by detecting the presence of a user. A camera is associated with the computer and the output from the camera is analyzed to determine if the user is present. If the user is present, then the computer is maintained in its non-power manage state. When the user leaves, however, the user's presence is no longer detected by the camera, and the power managed state can be quickly entered.

Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Abstract: A self-rewinding circuit includes a first block of combinatorial logic having a set of inputs including at least one input and a set of outputs including at least one output wherein a relationship between the set of inputs and the set of outputs is defined by a first input-output function. A first rewind circuit is coupled between the set of outputs and the set of inputs to implement an inversion of the input-output function.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.

Abstract: An approach for power reduction of an integrated circuit device. In response to detecting a change in an activity factor associated with an integrated circuit device from a first activity factor to a second activity factor, a supply voltage and a body bias associated with the integrated circuit device are adjusted based on the second activity factor to reduce power consumption. For one aspect, the supply voltage and body bias are adjusted to maintain a substantially constant operating frequency for the integrated circuit device.

Abstract: An integrated circuit device package. A substrate includes a first terminal coupled to the substrate. First and second conductive traces are formed on the substrate and are electrically coupled to the first terminal wherein the first conductive trace is provided to electrically couple a first bondwire to the first terminal and the second conductive trace is provided to electrically couple the second bondwire to the first terminal.

Abstract: A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately.

Abstract: A processor microarchitecture for efficient processing of instructions in a program including a program flow control instruction. The program flow control instruction specifies a target instruction and includes one or more candidate instructions between the target instruction and the program flow control instruction. A fetch unit fetches instructions in the program from the memory. Control logic stores one or more candidate instructions in the buffer prior to resolution of the conditional program flow control instruction in response to the fetch unit fetching a program flow control instruction specifying a target instruction within a predetermined number of instructions from the conditional program flow control instruction. In another embodiment, the candidate instructions are stored only if the conditional branch instruction is considered to be difficult to predict.

Abstract: A memory cell with vertically stacked crossovers. In prior memory cells, crossover connections within the memory cell were implemented in the same device layer. This wasted valuable design space, since the crossovers were therefore required to sit side-by-side in the layout design. The present invention implements crossovers in different materials on different device layers. The crossovers may therefore be vertically stacked on top of each other, reducing the area of the memory cell.

Abstract: A fuse sensing circuit comprises a first branch includes a first sensing transistor, and a fuse coupled to the source of the first sensing transistor. The fuse has a programmed state characterized by a first resistance, and an unprogrammed state in which the fuse has a second resistance. A second reference branch is coupled to the first branch in a current mirror configuration and includes a second sensing transistor, and a predetermined reference resistance coupled to the source of the second sensing transistor. The reference resistance is matched to the fuse device in an un-programmed state. The potential at an output node coupled to the first sensing transistor is determined by the state of the fuse device, such that the potential of the output node is within a first voltage range if the fuse device is programmed, and a second voltage range if the fuse device is un-programmed.

Abstract: A self-tracking sense amplifier strobing circuit and process to provide a sense amplifier enable signal in order to reliably control memory read operations over a wide variety of processing conditions. An array of self-tracking memory cells is configured to store a fixed value and includes at least a first tracking cell coupled to receive a wordline enable signal. First and second bitlines are coupled to the first array with the first bitline to be coupled to a power source. An output coupled to the second bitline is asserted to provide a sense amplifier enable signal when the second bitline reaches a predetermined voltage in response to the wordline enable signal being received by the tracking cell.

Abstract: An apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock that are substantially synchronous. The low-frequency clock is frequency divided-by-two to generate a LFdiv2 signal. The LFdiv2 signal is synchronously delayed by one phase of the high-frequency clock to generate a dLFdiv2 signal. The LFdiv2 and dLFdiv2 signals are compared using an XOR gate to generate a PH1 signal. A rising-edge of the PH1 signal indicates that a rising-edge of the high-frequency clock corresponds to a rising-edge of the low-frequency clock. This phase information allows enhanced communication between state machines or buses that are operating at different frequencies.

Abstract: Memory access control logic for controlling sequential and toggle mode burst accesses to a memory in a computer system using toggle mode automatic increment logic. The memory access control logic of the invention controls the sequence in which locations of a memory are accessed during a memory burst access operation wherein the burst access sequence is determined by an order in which a burst access starting address is incremented. Toggle increment logic for incrementing a starting address in a toggle sequence is included in the computer system in which the memory access control logic of the invention is used. An input bus receives a burst access request and a burst access starting address indicating a first memory location to be accessed in response to the burst access request from a device in the computer system. Additional logic determines whether the device requires a linear increment sequence or a toggle increment sequence for the burst access.

Abstract: A self-tracking write pulse control circuit to determine the time provided to complete a write operation to a memory. A tracking array including at least a first tracking memory cell configured on the memory includes an output and stores a default value. First and second bitlines are coupled to the tracking memory cell. A write multiplexor circuit is coupled to the first and second bitlines and coupled to receive an enable signal which concurrently initiates a write pulse. A write multiplexor circuit writes a different value to the tracking memory cell in response to receiving the enable signal. The output of the tracking memory cell transitions to end the write pulse when the different value has been successfully written to the tracking memory cell.

Abstract: A socket for coupling one of a first integrated circuit module having a first footprint and a first terminal array, or a second integrated circuit module having a second larger footprint to a printed circuit board. A socket base has a top surface for receiving one of the first and second integrated circuit modules and a bottom surface adapted to be mounted on a printed circuit board. A first array of contacts extends transversely through the base from the top surface to the bottom surface for electrically coupling the first terminal array to the printed circuit board. An alignment feature coupled to the base, is configured to align one of the first or second integrated circuit modules within the socket base such that the terminals of either the first or second integrated circuit modules engage the contact array, the second integrated circuit module extending beyond the alignment feature when aligned in the socket.