Abstract: An apparatus is disclosed which comprises an improved voltage driver circuit. Commonly available voltage driver circuits are deficient for driving n-channel MOS RAMs due to insufficient peak voltage and extended rise time. The apparatus, without requiring an additional voltage power supply or modifications to the memory system environment, effectively increases an internal drive voltage which results in the desired performance characteristics for driver circuits.

Abstract: A logic level translator uses a current switch, a current source and a plurality of cathode followers to convert T.sup.2 L and DTL level binary signals into CML and ECL level binary signals. The translator provides isolation between the T.sup.2 L ground and the CML ground so that noise in the CML signals is reduced.

Abstract: A comparator circuit compares the relative magnitudes of two binary numbers. Each of the binary numbers is fed in parallel through a plurality of two-bit comparator modules corresponding to the number of two-bit pairs in the largest binary number. The binary numbers are compared order by order and simultaneously to determine one or more of five relationships between the numbers. For binary numbers greater than two bits in length, the two-bit comparator module is utilized as the basic building block and an additional level of logic circuitry is required in order to obtain an output identifying one of the relationships. Since the two-bit modules may be used interchangeably and since the relative magnitude of any two-bit grouping is generated simultaneously, the comparator circuit provides for a fast and efficient identification of relationships between two binary numbers.

Abstract: Apparatus for utilizing a logical, record oriented move instruction is disclosed. By utilizing separately maintained data field descriptors which define the attributes of the data, the move instruction is able to transfer a multitude of different data types. From a source operand the logical instruction transfers data field by field to the destination. At the time of transfer, the logical move instruction reformats the data to meet the destination's description. The move instruction is applicable both to removing data from a data file and to restoring data into the data file.

Abstract: In a data processing system having independently operating asynchronous processors, apparatus is disclosed which provides for interprocessor synchronization and/or information exchange. Synchronization interlocks and controls are provided for both identifying shared resources of a control processor and an input/output controller (IOC) processor and for obtaining control over these shared resources. If a conflict situation for any one of the shared resources arises, apparatus is disclosed whereby the IOC processor is provided the capability of assuming control over the shared resource even though the central processor has control over it. One of the shared resources is an interprocessor communication register which allows communication of control information between both the central processor and the IOC processor and from the central processor to the peripheral processor over a shared bus.

Abstract: Apparatus for selectively producing at a single output terminal one of a plurality of pulse repetition frequencies (PRF) in response to a set of control signals. After decoding the control signals, the apparatus contains networks for delaying and gating affected clock drive pulse repetition frequencies. Apparatus output is a train of pulses whose PRF varies from time to time, but within a relatively narrow spectrum, under control of the decoded control signals. Such output signals are particularly useful for driving logical components in a computer system with highly specialized and sensitive system specifications.