Abstract: A display device having a plurality of select lines includes redundant select line scanners. Each scanner includes a plurality of substantially identical stages having an input terminal and an output terminal. The stages and select lines are ordinally numbered and correspondingly numbered stages are connected to opposite ends of the correspondingly numbered select lines by separate line segments. The stages within each scanner are cascaded by connecting the output terminal of each stage to the input terminal of the immediately succeeding stage. The select line scanners are independently operable by the provision separate power supplies and clock generators. During testing, one scanner is made to look like a high impedance to the scanner being tested. Failed stages of a scanner are replaced by the correspondingly numbered stage of the other scanner simply by opening the separate line segment of the failed stage.
Abstract: A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes an output circuit which switches the output terminal between high and low states. A first node switches the output terminal in response to an input signal and a second node keeps the output terminal low between the input pulse and a clocking pulse.
Abstract: A protection circuit for a solid state instrument includes a plurality of fuses and a switching device arranged in parallel with the input capacitance of the solid state instrument, The fuses protect the instrument from high voltage surges, and the switching device protects the instrument from lower voltage surges. The fuses and the switching device are solid state devices and thus can be fabricated along with the solid state instrument.
Abstract: A demultiplexer includes a plurality of transistors having conduction paths connected between an input terminal and output nodes. The control electrode of every transistor is connected to one line of a most significant bit bus by a first capacitive device, the control electrode of every transistor is also coupled to one line of a least significant bit bus by a second capacitive device. When the capacitive devices associated with the same transistor simultaneously receive an enable signal the transistor is turned on and current flows from the input terminal to an output node. Each transistor within the demultiplexer thus acts as a three state gate.
Abstract: A system for applying brightness signals to the pixels of a display device includes a transmission gate for each column of pixels. The control electrodes of the transmission gates are precharged to the threshold voltage of the gates to substantially increase the speed of the system. Comparators compare brightness voltages to a reference ramp voltage to enhance the speed and accuracy of the system.
Abstract: A record load-unload device has a curved guide device which engages the periphery of a record being inserted into and removed from said load-unload device. A friction drive member engages the edge of the record, and a drive device moves the record along the guide device for inserting and removing a record into and out of the load-unload device.
Abstract: A shift register includes transistors having conduction paths serially connected at a node and between an input terminal receiving a constant voltage and a clocked terminal receiving a clocked voltage of a first phase. The control electrode of one of the transistors receives a clocked voltage of a second phase and the control electrode of the other transistor receives an input signal. An inverter is arranged between the node and the output terminal.
Abstract: A pulse logic circuit comprises a plurality of interconnected stages. Each of the stages includes a relatively large node-charging transistor which, when enabled, forwards charging current to a node from a timing pulse of one of a plurality of phases applied to a load capacitance in series with the node-charging transistor. Such large transistors exhibit significant gate-to-source and gate-to drain distributed capacitances. The response time for charging a selected stage node can be decreased by precharging the gate of the node-charging transistor of a selected stage to enable the transistor prior to the application of a timing pulse, thereby increasing the maximum operating speed of the circuit. Disclosed species of such a pulse logic circuit include time vernier circuits which can be utilized as control circuitry for a liquid crystal television or computer display.
Abstract: A tensioned shadow mask/frame assembly includes horizontal top and bottom members and vertical side members. One of the horizontal members is permanently affixed to the side members and the other horizontal member is slideably supported on the side members. The horizontal members are biased apart to put tension on a shadow mask which is stretched across and permanently affixed thereto. The cross sectional configuration of the horizontal members is an acute angle having a long side and a short side joined at a rounded apex to maximize the stiffness of the members.
Abstract: A circuit for testing a liquid crystal display for open data lines, for identifying select lines shorted to data lines, and for identifying failed data line scanner stages includes thin film transistors arranged between each data line and a segmented bus. A sectioned shift register sequentially actuates the thin film transistors and the bus segments are monitored while data signals are applied to the data lines. The absence of a voltage on the bus indicates an open data line. The bus is also monitored while select signals are applied to the select lines and the shift register sequentially actuates the thin film transistors, the presence of a voltage on the bus indicates a short between a data line and a select line.
Abstract: A select line scanner circuit for a display device has a plurality of register stages. The register stages each include first and second register segments and first and second latch circuit means which receive select signals and apply oppositely poled logic signals to the output nodes of the register stages. Voltage boosting means are associated with at lest one of the register stages to assure that the logic signals are applied at the proper levels.
Abstract: An apparatus for transferring a kinescope and a chassis, which are coupled by cabling, from one location to another includes probes which engage apertures in the chassis to pick up the chassis. A frame supports suction cups to pick up the kinescope. The probes are supported by a bar which is pivotably attached to the frame. The chassis and kinescope are thus separately engaged and released but are simultaneously moved.
Abstract: A color picture tube includes a faceplate and a funnel attached to the faceplate. The faceplate has a horizontal dimension M.sub.h and a vertical dimension M.sub.v, with the dimensions having a ratio M.sub.h /M.sub.v greater than one. A magnetic shield is located within the tube. The magnetic shield has a front aperture in the proximity of the faceplate and a rear aperture remote from the faceplate. The front aperture has a horizontal dimension F.sub.h and a vertical dimension F.sub.v and the rear aperture has a horizontal dimension R.sub.h and a vertical dimension R.sub.v. The top and bottom of the rear aperature are close to the sides of the funnel and the sides of the rear aperture are spaced from the funnel by a spacing consistent with the entrance of the electron beams at maximum deflection into the shield.
Abstract: A liquid crystal pixel electrode and a thin film transistor (TFT) structure includes a select line, a portion of which is coated with undoped solid state material. The select line is parallel to a continuous uninterrupted side of the pixel electrode and a data line is parallel to another continuous uninterrupted side of the pixel electrode. A source area and a drain area of doped solid state material are placed over the undoped layer. The source area contacts the data line and the drain area contacts the pixel electrode. The select line also serves as the gate electrode of the TFT. A notch passes through the undoped material between the data line and the drain to prevent leakage.
Abstract: An enclosure for a television receiver is composed of a base member, a cover member and a bezel member which are joined into a stiff triangular enclosure which supports the receiver tube and protects the tube from implosion because of impacts.
Abstract: An alignment layer for a liquid crystal display device provides optimum molecular alignment, tilt angle and resistivity by depositing a glow discharge layer comprised of carbon, nitrogen, and hydrogen onto the electrodes of the liquid crystal cell.
October 30, 1989
Date of Patent:
May 7, 1991
General Electric Company
Grezgorz Kaganowicz, Frank P. Cuomo, Leon J. Vieland
Abstract: An alignment layer for a liquid crystal display device which provides optimum molecular alignment, tilt angle and resistivity is formed by depositing, using glow discharge, an inorganic silicon based material onto the electrodes of the liquid crystal cell.
Abstract: The adherence of the alignment layer of a liquid crystal cell is improved by simultaneously glow discharging and sputtering the alignment materials onto the conductors and substrates of the liquid crystal cell.