Abstract: An arrangement for achieving multi-processing is disclosed for use in a communication system where it is desired to have several independent processors operating in parallel on stimuli received from the connected terminals. Each such terminal is associated with a particular processor and that processor serves to control connections involving its associated stations. Stimuli from the station are stored in a queue and processed in an intermixed fashion such that stimuli from the connection are processed in order of arrival of the stimulus, but stimuli from different connections are processed without regard to the relative order of arrival of stimuli between connections.

Abstract: There is disclosed a speech interface circuit for use with a communication bus to interface telephone users with a computer which is also connected to the communication bus. The circuit operates to accept digital input signals over the bus from the communication processor as well as from the user and to translate these signals for the benefit of the computer. Under control of computer instructions interpreted from the translated signals, the interface transmits selected prestored speech messages to calling users.

Abstract: There is disclosed an arrangement for testing each portion of a system by stimulating at an interface of the system the expected responses. Software scripts are pregenerated and compiled into system message commands. Each script contains sequences of expected message responses as well as stimuli messages. The system is designed to use a single interface without regard to the type of simulated messages.