Patents Represented by Attorney D. I. Caplan
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Patent number: 5701152Abstract: Only one or only a few channels are sent at a time from curbside circuitry located in a curbside box, via a link such as either a coaxial or a fiber cable, into a customer's home TV set or personal computer. However, many more than a few channels are delivered to the curbside box from a central office or a central bank of paid video-movies to be selected by the customers. The curbside box serves a multitude of homes, a separate (narrow-band) cable running to each home from the (same) curbside switch. Each channel can be a free radio or free TV channel, a stored or an on-line newspaper pay channel, or a pay TV channel, or a pay-per-view channel. Requests from each TV set in each home (e.g., initiated by a hand-held remote control infra-red sending device) can be sent to the curbside circuitry from the home along a link such as a wire or along the same curbside-to-home cable itself. Storage of billing information with respect to each customer is accomplished by a billing recorder located in the curbside box.Type: GrantFiled: September 28, 1995Date of Patent: December 23, 1997Assignee: Lucent Technologies Inc.Inventor: Howard Zehua Chen
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Patent number: 5534802Abstract: A sample-and-hold circuit is formed in bipolar transistor technology with the aid of clocked and complementary-clocked bipolar transistors in combination with a holding capacitor whose output terminal, in going from sample to hold phases of the clock, undergoes change in voltage .DELTA.V equal to the input voltage samples Vin applied to its input terminal during the sample phases (electrical bootstrapping operation). In particular, an input terminal of the holding capacitor is connected to a clocked input voltage device that ensures that, during the sample phases, the input voltage applied to the input terminal of the capacitor represents the input voltage being sampled, and that during the hold phases of the clock, the input terminal of the capacitor is electrically clamped. An output terminal of the holding capacitor is connected to one of the clocked transistors and to an auxiliary bipolar transistor whose base terminal is controlled by a complementary-clocked voltage-dropping device.Type: GrantFiled: September 1, 1994Date of Patent: July 9, 1996Assignee: AT&T Corp.Inventor: Behzad Razavi
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Patent number: 5334306Abstract: A graphite path is formed along the surface of a diamond plate, preferably a CVD diamond plate, by means of a laser or ion-implantation induced conductivity. The path advantageously can be the surface of a sidewall of a via hole drilled by the laser through the plate or a path running along a side surface of the plate from top to bottom opposed major surfaces of the plate. The graphite path is metallized, as by electroplating or electroless plating. In this way, for example, an electrically conducting connection can be made between a metallized backplane located on the bottom surface of the plate and a wire-bonding pad located on the top surface of the plate.Type: GrantFiled: November 19, 1992Date of Patent: August 2, 1994Assignee: AT&T Bell LaboratoriesInventors: William C. Dautremont-Smith, Leonard C. Feldman, Rafael Kalish, Avishay Katz, Barry Miller, Netzer Moriya
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Patent number: 5232873Abstract: A semiconductor device substrate has a major surface on which is located an insulating layer, such as silicon dioxide, having an aperture penetrating through it all the way down to the major surface. An impurity-doped plug, such as tungsten doped with zinc, is spatially selectively deposited in the aperture to a thickness such that the height of the plug is significantly less than the height of the aperture in the insulating layer, by means of a rapid-thermal-cycle low-pressure-metalorganic-chemical vapor deposition (RTC-LP-MOCVD) process. Then another plug, of (pure) conductive barrier metal such as tungsten, is deposited on at least the entire top surface of the impurity-doped plug and on the sidewalls of the insulating layer. The structure being fabricated can then be heated, in order to diffuse the impurity into the underlying semiconductor device substrate.Type: GrantFiled: October 13, 1992Date of Patent: August 3, 1993Assignee: AT&T Bell LaboratoriesInventors: Michael Geva, Avishay Katz
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Patent number: 5197654Abstract: A device such as a laser is bonded to a submount such as diamond by a process in which the submount is successively coated with an adhesion layer such as titanium, a barrier layer such as nickel, and a gold-tin solder-metallization composite layer formed by sequential deposition on the barrier layer a number (preferably greater than seven) of multiple alternating layers of gold and tin, the last layer being gold having a thickness that is equal to approximately one-half or less than the thickness of the (next-to-last) tin layer that it contacts immediately beneath it. The bonding is performed under applied heat that is sufficient to melt the solder-metallization composite layer. Prior to the bonding, (in addition to the submount) the device advantageously is coated with gold and optionally with a similar gold-tin solder-metallization composite layer, at least at locations where it comes in contact with the gold-tin solder-metallization composite layer.Type: GrantFiled: November 15, 1991Date of Patent: March 30, 1993Inventors: Avishay Katz, Chien-Hsun Lee, King L. Tai, Yiu-Man Wong
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Patent number: 5162753Abstract: An amplifier arrangement suitable for use as a line driver is built with a Class AB stage connected in parallel with a Class B stage, whereby the output currents of the stages are summed. Each of the Class AB and the Class B stages has an output current device that is connected in a common-source configuration.In a push-pull configuration of the arrangement, each of a pair of operational amplifiers in the Class AB stage separately drives each of a pair of operational amplifiers in the Class B stage.Type: GrantFiled: November 27, 1991Date of Patent: November 10, 1992Assignee: AT&T Bell LaboratoriesInventor: Haideh Khorramabadi
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Patent number: 5153083Abstract: Phase-shifting (two-optical-level) masks are manufactured by a self-aligned technique in which after first-level trenches in the mask have been formed, second-level trenches therein are formed by patterning an electron resist overlying the mask in such a manner that the edges of the patterned resist can be located anywhere within the first-level trenches, whereby the need for precise alignment of the resist patterning for the second-level trenches is avoided.Type: GrantFiled: December 5, 1990Date of Patent: October 6, 1992Assignee: AT&T Bell LaboratoriesInventors: Joseph G. Garofalo, Robert L. Kostelak, Jr., Sheila Vaidya
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Patent number: 5057455Abstract: In the fabrication of electrodes for transistors in the BiCMOS integrated circuit, vertical windows etched in a relatively thick TEOS (or other suitable dielectric) layer, located on a relatively thin polysilicon layer, in turn located on relatively tin oxide layer areas and on relatively thick oxide layer areas, are used to define areas where polysilicon electrode material is to remain. Polysilicon is deposited in the windows in the relatively thick insulating layer, to form the basis for the desired electrode in each window. The relatively thin polysilicon layer (or, alternatively an .alpha.-amorphous silicon layer) is thereafter used as an etch stop during the subsequent removal of the relatively thick dielectric layer. Thereafter both MOS and bipolar transistors can be fabricated using the windows to define the extents of the gate regions of the MOS transistors and the extents of the emitter regions of the bipolar transistors.Type: GrantFiled: November 30, 1989Date of Patent: October 15, 1991Assignee: AT&T Bell LaboratoriesInventors: Pang-Dow Foo, William T. Lynch, Chien-Shing Pai
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Patent number: 5030926Abstract: A voltage controlled crystal oscillator circuit, such as a Pierce oscillator circuit, includes an amplifier and is balanced by the addition of another varactor connected directly to the amplifier, whereby the frequency pull range is increased. Further, greater linearity can be achieved by adding another pair of varactors to the circuit.Type: GrantFiled: July 10, 1990Date of Patent: July 9, 1991Assignee: AT&T Bell LaboratoriesInventor: Robert W. Walden
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Patent number: 5023673Abstract: A semiconductor multiple quantum well mesa structure, for use as the optically active element in an optical logic or an optically controlled optical switching device, has its side surfaces implanted with surface recombination centers, whereby the optical switching speed is increased.Type: GrantFiled: July 21, 1989Date of Patent: June 11, 1991Assignee: AT&T Bell LaboratoriesInventors: Samuel L. McCall, Jr., Kuochou Tai
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Patent number: 5023198Abstract: A quaternary semiconductor diffraction grating, such as an InGaAsP grating suitable for a DFB laser, is embedded in a semiconductor substrate, such as InP. In one embodiment, the grating is fabricated by(1) forming on the top surface of an InP substrate body an epitaxial layer of InGaAsP coated with an epitaxial layer of InP;(2) forming a pattern of apertures penetrating through the layers of InP and InGaAsP; and(3) heating the body to a temperature sufficient to cause a mass transport of InP from the InP epitaxial layer, the thickness of the InP layer being sufficient to bury the entire surface of the InGaAsP layer with InP.Type: GrantFiled: February 28, 1990Date of Patent: June 11, 1991Assignee: AT&T Bell LaboratoriesInventor: Keith E. Strege
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Patent number: 5018157Abstract: In a vertical cavity laser, such as an InP based vertical laser, the energy bandgap in the active region can be made equal to or larger than the bandgap in a semiconductor mirror stack by virtue of degenerate doping in the stack sufficient to suppress electronic band-to-band optical absorption. For example, the active region of an InP based laser can be lattice-matched GaInAs, GaInAsP, or a multiple quantum well structure composed of layers of InP and GaInAs--with the mirror stack composed of alternating layers of InP and degenerately doped n-type lattice-matched GaInAs or GaInAsP.Type: GrantFiled: January 30, 1990Date of Patent: May 21, 1991Assignee: AT&T Bell LaboratoriesInventors: Dennis G. Deppe, Russell D. Dupuis, Erdmann F. Schubert
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Patent number: 5012486Abstract: In a vertical semiconductor laser, the top mirror is composed of alternating layers of lattice-mismatched semiconductors. Quantum reflections and other charge transport barriers for majority carriers at the interface, and hence electrical resistance and power dissipation, are reduced by choosing the lattice-mismatched semiconductor materials in such a manner as to align their band edges for majority carriers. On the other hand, the semiconductor materials are selected to supply relatively large refractive index differences, and hence relatively large optical reflections, at their interfaces. The lattice-mismatching may also produce vertical thread dislocations through the stack, which increase the electrical conductivity.Type: GrantFiled: April 6, 1990Date of Patent: April 30, 1991Assignee: AT&T Bell LaboratoriesInventors: Sergey Luryi, Ya-Hong Xie
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Patent number: 4999485Abstract: A nonlinear optical device structure is formed by a compound semiconductor having a graded chemical composition such that the average drift velocity of electrons is in the same direction as, but of greater magnitude than, that of holes. In this way, when a pump optical beam (control beam) is flashed (as by a picosecond pulse) upon the structure, electron-hole pairs are created with a resulting temporary spatial separation between the holes and the electron--whereby an electric dipole moment is temporarily induced in the structure. In turn, this dipole moment temporarily modifies either the birefringence or absorption property, or both, with respect to a controlled beam--whereby the polarization, phase, or intensity, of the controlled beam can be modified by the control beam. After the electrons and holes drift to positions which extinguish the dipole the structure is ready for a repeat performance.Type: GrantFiled: June 4, 1990Date of Patent: March 12, 1991Assignee: AT&T Bell LaboratoriesInventors: Federico Capasso, Stephen E. Ralph
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Patent number: 4999843Abstract: A vertical laser is typically formed by successive horizontal layers, epitaxially grown on a substrate, suitable for forming a bottom mirror, a bottom cladding layer, an active region, a top cladding layer, and a top mirror. In prior art, one of a pair of electrodes for enabling electrical pumping the laser--the "top" electrode--is attached to the top surface of the top mirror, whereby undesirably large amounts of heat are generated because of the relatively high impedance of the top mirror. To reduce this heat generation, the laser is redesigned to enable the top electrode to make lateral contact with the top cladding layer, whereby the impedance and hence the power loss are reduced.Type: GrantFiled: January 9, 1990Date of Patent: March 12, 1991Assignee: AT&T Bell LaboratoriesInventors: Sergey Luryi, Ya-Hong Xie
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Patent number: 4999808Abstract: In order that a microprocessor can respond properly to both instruction words and data words that are organized in off-chip memory in accordance with either of two byte order conventions, on-chip circuitry is added which controllably changes the byte order of both the instructions and the data to that of the microprocessor.Type: GrantFiled: October 5, 1989Date of Patent: March 12, 1991Assignee: AT&T Bell LaboratoriesInventors: Donald E. Blahut, Brian W. Colbry, Thomas D. Lovett, Peter V. LaMaster
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Patent number: 4992394Abstract: In order to reduce alignment errors arising in the fabrication of semiconductor integrated circuits using electron beam lithography, enhanced registration marks--(i.e., registration marks that are more easily and accurately detectable by the electron beam)--are formed at the edges of oxide layers, located at the surface of a silicon body, by means of forming metal silicide layers having edges coincident with the edges of the oxide layers. Advantageously, the enhancing of the registgration marks by forming the metal silicide is performed subsequent to any high temperature processing steps, whereby the integrity of the marks is maintained.Type: GrantFiled: July 31, 1989Date of Patent: February 12, 1991Assignee: AT&T Bell LaboratoriesInventors: Robert L. Kostelak, Jr., William T. Lynch, Sheila Vaidya
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Patent number: 4985373Abstract: Insulation between first and second levels of aluminum metallization in semiconductor integrated circuit structures comprises a plasma planarized, deposited silicon dioxide layer and another silicon dioxide layer deposited upon said plasma planarized layer.Type: GrantFiled: May 24, 1989Date of Patent: January 15, 1991Assignee: AT&T Bell LaboratoriesInventors: Hyman J. Levinstein, William D. Powell, Jr., Ashok K. Sinha
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Patent number: 3985447Abstract: In order to measure the thickness and refractive index of a thin film on a substrate, such as a film of silicon dioxide on a substrate of silicon, a beam of substantially monochromatic polarized light is directed on the film. The reflected light is transmitted through an optical compensator and an optical analyzer both of which are rotating at different angular speeds, .omega..sub.A and .omega..sub.C, respectively; and the transmitted optical intensity is measured as a function of time. A Fourier analysis, for example, of the profile of this optical intensity vs. time can then be used for determining the Stokes parameters of the light reflected by the thin film and thereby also the thickness and refractive index of the film.Type: GrantFiled: August 29, 1975Date of Patent: October 12, 1976Assignee: Bell Telephone Laboratories, IncorporatedInventor: David Erik Aspnes
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Patent number: 3986059Abstract: A charge regenerator for a semiconductor charge transfer device is disclosed in which the regenerator contains an input diode which is subjected to a pulsed voltage. The signal to be regenerated is applied to a control gate electrode which controls the surface potential of the underlying semiconductor surface region located between the input diode and an auxiliary transfer cell feeding an array of output charge transfer cells. After termination of the diode pulse, charges flow back from the auxiliary transfer cell to the input diode through the control gate region such that the charge remaining in the auxiliary transfer cell is independent of the signal level on the control gate so long as this signal level is above a threshold for the injection of charges from the input diode to the auxiliary transfer cell and is zero otherwise.Type: GrantFiled: April 18, 1975Date of Patent: October 12, 1976Assignee: Bell Telephone Laboratories, IncorporatedInventor: Amr Mohamed Mohsen