Abstract: Digital phase shifter, comprising series connection of controlled phase shifting bits (3a-3k), each of them inserts determinate amount of phase delay of the passing signal, wherein the phase change occur in response to the control signal switching the phase cells 3k and applied to its steering terminal 4k for a switching element (11, 21, 22, 31, 32) of each of the cells 3, characterized in applying as a switching element (11,21,22,31,32) the discrete p-HEMT (pseudomorphic high electron mobility transistors) with positive or negative pinch-off voltage.