Abstract: A signal compression-selection arrangement (19) dynamically trades off signal storage capacity against signal quality, by sacrificing capacity in favor of signal quality whenever capacity is plentiful and sacrificing quality in favor of capacity whenever capacity is scarce. In a messaging system (FIG. 1), the arrangement monitors the amount of storage (14, 15) that is presently free and available for storing new messages, either on a system-wide or per-mailbox basis, and automatically selects a higher compression rate (13) than a presently-applied compression rate (13) to be applied to newly-received messages as the amount of free storage falls below each predetermined threshold. Storage capacity may be freed up by re-compressing (FIG. 3) at the new, higher, compression rate those stored messages that were previously compressed at a lower compression rate.

Abstract: A telephone station set (100) alerting arrangement preferably uses a a speakerphone loudspeaker (140) to produce audible alerting signals (e.g., ringing signals )from locally-generated (105, 115) alerting signals both when the set is on-hook and when the set is off-hook. The present state of the speakerphone control circuit (102) is used to control the volume of the produced audible alerting signals: high-volume alerting signals are supplied to the loudspeaker when the control circuit (102) is used to control the volume of the produced audible alerting signals: high-volume alerting signals are supplied to the loudspeaker when the control circuit is in talking state (202), and low-volume, attenuated alerting signals are supplied to the loudspeaker when the control circuit is in listening state (201). The appearance of alerting signals when the speakerphone control circuit is in idle state (200) causes the speakerphone circuit to make a transition to the talking state.

Abstract: A processing system (10) includes a backplane bus (13) that defines a plurality of locations (20-31) implemented as backplane slots each for connecting any option module (41) thereto. Each slot includes contact pins (201a-d) that carry binary logic levels forming a different digital number at each slot. Option modules include their own source of timing signals (220) comprising an oscillator (221) and an identical thermally-sensitive crystal (222) for driving the oscillator. Each option module includes receptacles (207a-d) for the contact pins. The receptacles are connected to the digital input port of a D/A converter (225) whose output port is connected to a heater (224) mounted in physical proximity to the crystal in the crystal's case (223). Depending on which slot an option module is mounted in, the D/A converter receives a different digital input and hence generates a different level of output.

Abstract: A cache memory system reduces cache interference during direct memory access block write operations to main memory. A control memory within cache contains in a single location validity bits for each word in a memory block. In response to the first word transferred at the beginning of a direct memory access block write operation to main memory, all validity bits for the block are reset in a single cache cycle. Cache is thereafter free to be read by the central processor during the time that the remaining words of the block are written without the need for additional cache invalidation memory cycles.

Abstract: Disclosed is a method and apparatus for avoiding accessing of defective locations in disks and other storage media. A disk file controller uses manufacturer-provided information about the location of defects to construct a sequentially ordered list of addresses of defective storage locations in the disk, and the list is stored in a table in the disk. During use of the disk, the disk file controller reads the table of defects into its memory and uses it to translate virtual addresses into real addresses. The translation process skips over real addresses of defective locations. The virtual address is translated into a real address by being incremented by the number of defects whose addresses are lower than the real address. Subsequent contiguous virtual addresses are translated into real addresses by being incremented by the number of contiguous defective locations that follow the location associated with the preceding virtual address.

Abstract: In a communication system which includes a plurality of stations interconnected for communications by a first bus, a second station includes a device, such as a processor, and a resource, such as a memory or a peripheral unit, interconnected for communication by a second bus. An interface mechanism connecting the first bus with the second bus allows the device to access the first bus over the second bus, and allows a first station to access the resource via the first and second buses. Deadlock detection circuitry detects cotemporaneous attempts by the device to access the first bus and attempts by the first station to access the resource. Deadlock resolution circuitry responds to deadlock detection by disconnecting the device from the second bus to allow the first station to access the resource, and by reconnecting the device to the second bus when the first station ceases to access the resource.

Abstract: A synchronous apparatus synchronized to the operation of the slowest device is disclosed, comprising a plurality of devices such as first-in first-out buffer memories (FIFOs) connected to at least one synchronizing mechanism such as a full adder circuit. Each device generates a signal to indicating readiness to operate and a signal indicating completion of operation. Each device receives a signal causing the device to operate and a signal causing the device to stop operating. The synchronizing mechanism generates the operate signal upon sensing the readiness signals of all the devices and continues to generate the operate signal while at least one of the ready signals is sensed. The synchronizing mechanism generates the stop signal upon sensing the completion signal from all of the devices and continues to generate that signal while at least one of the completion signals is sensed.

Abstract: An improved multipoint access data communication system with collision detection provides a duplicative communication medium, network interface units adapted for connection to transceivers on both media, transceivers adapted for connection to a plurality of network interface units, and a local collision detection circuit associated with each transceiver for detecting collisions between transmissions simultaneously attempted by two or more network interface units connected to the transceiver.