Abstract: A system for reading out the contents of multiple counters onto a common bus comprising a plurality of synchronous binary counters arranged in a ring with each counter having N corresponding stages each having an output terminal on which appears the contents of the stage, an input terminal, and a clock pulse input terminal, with each stage responsive to a clock pulse supplied to its clock input terminal to transfer the signal logic level on its input terminal to its output terminal and with the output terminals of the stages of a given counter comprising the common bus. Also provided is a clock pulse source for supplying clock pulses to all of the clock input terminals and a switching signal source for generating a switching pulse. A switch associated with each stage is responsive to the switching pulse to connect the output terminal of each stage to the input terminal of the corresponding stage of the next adjacent counter in the ring of counters.
October 13, 1981
Date of Patent:
October 16, 1984
Steve J. Nossen, Stanley S. Brokl, Kenyon E. B. McGuire
Abstract: A system for detecting phase lock loss between first and second two level signals S.sub.N and S.sub.R, and comprising an Exclusive OR (XOR) gate having first and second input terminals and an output terminal, logic for supplying S.sub.N and S.sub.R to the first and second inputs of the XOR gate so that the center points of the respective upper and lower levels are aligned and with the time intervals between adjacent leading and trailing edges of S.sub.N and S.sub.R being nominally equal to .DELTA.t. Also provided is an AND gate having first and second input terminals and an output terminal, and delay logic for supplying the output signal of the XOR gate to the two input terminals of the AND gate with such output signal arriving at one of the input terminals of the AND gate a time interval .DELTA.t after the arrival of the output signal at the other input terminal of the AND gate and a detector for detecting an output signal from the AND gate to indicate loss of phase lock.
Abstract: An improvement in a frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S.sub.VCO of frequency F.sub.VCO, a divider for dividing F.sub.VCO in division cycles with each division cycle consisting of the division of F.sub.VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S.sub.N of frequency F.sub.N, where the division ratio is ##EQU1## and where N, Y, M and Z are integers, a reference signal generator for generating a reference signal S.sub.R of frequency F.sub.R, and a phase detector responsive to S.sub.N and S.sub.R to produce an output signal whose amplitude is representative of the phase therebetween. The improvement is a control circuit comprising logic for detecting and averaging the output signal from the phase detector during each division of F.sub.VCO in each division cycle to produce a d.c.
Abstract: An improvement in a digital frequency synthesizer comprising a voltage-controlled oscillator (VCO) for producing a signal S.sub.VCO having a frequency f.sub.VCO, a first signal generator for generating a plurality of signals S.sub.AS having a spectrum of frequencies f.sub.AS, all exceeding a given minimum frequency f.sub.M, a mixer responsive to S.sub.VCO and to S.sub.AS to produce an output signal having a frequency (f.sub.VCO .+-.f.sub.AS), a divide-by-N divider responsive to (f.sub.VCO .+-.f.sub.AS) to produce a signal S.sub.N having a frequency f.sub.N, a second signal generator for generating a first reference signal S.sub.R1 having a frequency f.sub.R1, a phase detector responsive to S.sub.N and S.sub.R1 to produce a d.c. control signal E.sub.c whose amplitude varies with the phase relation of S.sub.N and S.sub.R1, and a filter for supplying E.sub.c back to said VCO, the VCO being responsive to E.sub.c to produce an output signal S.sub.VCO of frequency f.sub.VCO where (f.sub.VCO .+-.f.sub.AS )=Nf.sub.
Abstract: An improvement in a phase locked loop comprising a VCO for generating a signal S.sub.VCO of frequency f.sub.VCO, a divider for dividing f.sub.VCO to produce a signal S.sub.N of frequency f.sub.N, a reference signal generator for generating a reference signal S.sub.R of frequency f.sub.R, and with said VCO responsive to a particular value E.sub.c of a variable control signal e.sub.c to cause f.sub.N =f.sub.R for a given value of N, the improvement consisting of a phase/frequency detector for detecting and correcting frequency and phase differences between S.sub.N and S.sub.R to cause f.sub.N =f.sub.R and comprising a three stage left/right shift register responsive to one of signals S.sub.N or S.sub.R to shift binary O's into the first stage thereof in the right direction and responsive to the other of signals S.sub.N or S.sub.R to shift binary 1's into the third stage thereof in the left direction.
Abstract: A decoder for reconstructing a standard composite video signal with standard synchronizing pulses from a video signal V with only gray sync encoding E.sub.GS, of a repetition rate f.sub.GS, and comprising a first generator for generating a signal E.sub.VCO having a controllable frequency f.sub.VCO which, in the absence of frequency control, is slightly different from f.sub.GS, a second generator responsive to E.sub.VCO to form a composite blanking signal E.sub.B having a repetition rate equal to f.sub.VCO so that E.sub.B will slew with respect to E.sub.GS until E.sub.B and E.sub.GS become synchronized and a summer for summing E.sub.B and V to produce a reconstructed standard composite video signal when E.sub.B and E.sub.GS become synchronized. There is further provided a phase lock circuit for phase locking E.sub.VCO with the standard synchronizing pulses of said reconstructed video signal to maintain E.sub.B and E.sub.GS in a synchronized relationship.
Abstract: A velocity control system for a rotating disc having a spiralling track thereon and comprising an arm rotatable about a fixed axis, a stylus attached to such arm and positioned to follow the spiralling track, and logic responsive to the position of the arm to produce a control signal indicative of the position of the arm. Also provided is a prime mover responsive to the control signal to rotate the disc at an angular velocity to produce a velocity at the point of contact between the stylus and the disc which is a predetermined function of the position of the stylus.
Abstract: A data processor system having a total memory capacity, an integrated circuit chip having thereon a central processing unit (CPU), a ROM, a RAM, a first decoder responsive to addresses supplied thereto for determining the location of the RAM in the total memory capacity, and logic for disabling the ROM from the CPU and for relocating the RAM in the total memory capacity. Also provided are a generator for generating a first control signal having first and second states, first gating logic responsive to the first state of the control signal to disable the ROM and to disconnect the output of the first decoder from the RAM.
Abstract: In a data processing system having a memory and employing N-bit bytes and two byte addresses, a branch instruction which can cross one page boundary is executed without having to use calculations to effect a change in the contents of the program counter (PC). It is determined whether the value V1 of the (N-1) least significant bits (LSB's ) of the lower order byte of the two byte branch address is greater or less than the value V2 of the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing and also whether PC N.noteq.BR N where PC N and BR N are the most significant bits of the lower order bytes of the PC address and the branch address, respectively. If V1<V2, PC N=1, and PC N.noteq.BR N, the upper order byte of the PC address is incremented by 1 and if V1>V2, PC N=0, and PC N.noteq.BR 7, the upper order byte of the PC address is decremented by 1.
Abstract: A method and apparatus for the adaptive equalizing of phase and amplitude distortion in a received signal by an N-stage digital delay line system and comprising the steps of digitally sampling the received signal and advancing each digital sample through successive stages of the N-stage digital delay line, producing a continuously up-dated scaled error signal after each advance of the digital samples in the delay line, multiplying the digital sample in each delay line stage by the scaled error signal after each sampling advance to produce a first scaled signal in each stage, separately accumulating the first scaled signals of each stage after each sampling advance, scaling and accumulating the accumulations of the first scaled signals of each stage after each M accumulations thereof to produce a weighting tap signal for each stage of the delay line, multiplying the received samples by the weighting tap signal of each stage to produce a weighted sampling for each stage, summing the weighted samplings to produc
Abstract: An improved automatic gain control system for a frequency modulated television (FM/TV) transmitter transmission system comprising a transmitter for generating and transmitting a television (TV) signal, a satellite repeater, and at least one receiver having a demodulator and which collectively form a transmission path having a certain frequency bandwidth with the transmitter comprising a pre-emphasis circuit for pre-emphasizing the TV signal and an FM circuit for frequency modulating the output of the pre-emphasis circuit. The invention provides a filter located at the transmitter for simulating the filter characteristics of the overall transmission path and responsive to the frequency modulated TV signal generated at the transmitter to produce a control signal in the event the spectrum of the frequency modulated TV signal exceeds the transmission path bandwidth.
Abstract: Milling machine apparatus and method for controlling the relative movement between a working surface and a cutting edge in which said relative movement approximates a mathematically definable path and occurs in a series of line segments each intersecting said path at first and second points with the second point of each line segment being the first point of the next successive line segment. The system comprises first means for determining a maximum distance d' between each successive line segment and said path measured along a line extending from a predetermined reference and passing between said first and second points, where d'=d+.DELTA.d, a predetermined range of value. Also provided are second means responsive to the determination of d' for each successive line segment to then establish the first point of intersection of the next successive line segment, and control means responsive to the determined points of intersection to generate prime moving control signals.
Abstract: A bistable solid-state device, substantially immune to long term, low level radiation comprises, in combination with memory storage elements, means comprising P-type devices responsive to enabling and disabling signals for conducting signals to and from the memory storage elements only during the presence of read and write signals, and which are substantially immune to the effects of long term, low level radiation, thereby substantially increasing the reliability of solid-state memory cells. Also provided are means for generating a control signal having first and second levels and logic means responsive to said control signals of a first level to generate and supply said enabling signal to said P-type device and further responsive to said control signal of a second level to generate and supply said disabling signal to said P-type device. Sensing means for sensing the state of said bistable memory elements during a time period between successive level changes of said control signals is also provided.
May 13, 1981
Date of Patent:
November 29, 1983
William F. Heagerty, Gerald T. Caracciolo, William F. Gehweiler
Abstract: An expandable scaler for scaling an N bit digital word. The system comprises first and second scalers each of which comprises N input terminals for receiving an N bit word, N output terminals, and (x+1) corresponding groups of first switching logic to form (x+1) corresponding pairs of groups of first switching logic with each group having input terminals and output terminals and being arranged in successive manner with the output of each of the first (x) groups being connected in parallel manner to the input terminals of the next successive group and where 2.sup.x =N, and leads for supplying the N bit digital input word to the input terminals of the group of first switching logic and further with each pair of corresponding groups of switching logic means responsive to an enabling signal to selectively shift the N bit digital input word by one of 2.sup.o, 2.sup.1,-2.sup.x =m bit positions.
Abstract: A system for detecting the successful detection of a known serial data sequence of L bits. The system comprises clock pulse generating means for generating a train of clock pulses at a rate f.sub.c, shift register means having N stages each with an output terminal for serially receiving said data sequence at said clock pulse rate fc and for supplying the contents of each stage to the output terminal thereof, and memory means having at least M output terminals, N+M input terminals, and X memory locations each accessable by a predetermined address supplied to said input N+M terminals to supply the contents of said memory location to said M output terminals. Further provided is a latch having at least M input and output terminals and responsive to the signals on the M output terminals of said memory means to supply such signals back to the M input terminals of said memory means a time interval .DELTA. after the entering of a bit of said serial data sequence into said shift register means, where .DELTA.<1/f.
Abstract: An improved automatic gain control (AGC) for a television transmission system comprising a transmitter for transmitting a TV signal via a transmission path to a receiver and having a certain bandwidth in which said transmitter includes a generator for generating a baseband TV signal which can be pre-emphasized, and a variable gain amplifier responsive to the baseband TV signal to produce an amplified baseband video signal. The AGC system comprises a band eliminating filter responsive to the baseband output signal to produce a control signal whose amplitude reflects the change in energy content of that portion of the TV output signal lying outside the allowed transmission bandwidth. The variable gain amplifier is responsive to the control signal to vary its gain substantially inversely as the out-of-band energy content varies. At the receiver a detector detects a component of the received TV signal which has known characteristics, usually constant, in the absence of the gain introduced at the transmitter.
Abstract: Circuit and method for synchronizing a clocked coded output signal with an iterative encoded input signal in a time relation that results in the greatest correlation. An AS (arithmetic synthesizer) initially produces a clock signal at a rate different from that of the input signal. The clock signal so produced drives a waveform generator that produces an iterative encoded signal similar in kind to the input signal. As the time (phase) relation between the generated signal and the input signal is varied, a correlation coefficient is derived at successive phase positions. The AS is then set into the condition of greatest correlation and synchronized with the input signal.
Abstract: Multi-contact electrical connector comprises a housing and cover members. The housing has a mating end, a rearward end, and laterally facing sides which extend between the mating and rearward ends. Contact terminals are contained in the housing and arranged in parallel rows which extend across the laterally facing sides. Each terminal has a wire-receiving portion which is dimensioned to receive a wire and establish electrical contact therewith upon movement of the wire laterally of its axis and into the wire-receiving portion. An electrical commoning means extends across the sides of the housing adjacent to the rearward end thereof and also has spaced-apart wire-receiving portions for reception of ground wires in a cable. The cover members are dimensioned such that they can be assembled to the side surfaces of the housing and each cover member has wire-receiving grooves or channels therein in which the wires of the cable can be positioned prior to assembly of the cover members to the housing.
February 18, 1977
Date of Patent:
June 13, 1978
Frank Peter Dola, Frederick William Rossler, Jr.
Abstract: A two part connector system for connecting a circuit element such as an integrated circuit chip to the surface of a printed circuit board in which the first connector section, e.g., a chip carrier, which holds the circuit chip, has resilient, spring-like external terminals which can be connected directly and permanently on the printed circuit board surface, as by soldering, without appreciable risk of breakage of said connections because of different expansion and contraction coefficients of the chip carrier and the printed circuit board or, alternatively, the chip carrier can be removably mounted in the second connector section, e.g., a socket, which also has resilient, spring-like external terminals connectable permanently to the surface of the printed circuit without appreciable risk of breakage of said connections because of different expansion and contraction coefficients of the socket and the circuit board.
Abstract: An electrical terminal structure is disclosed which is provided with a flow deposited quantity or band of solder adhered to a selected portion of the terminal and limited from spreading over the surface of the terminal by the presence of a solder-nonwettable material adjacent to but not necessarily touching the terminal. A method of mounting the banded electrical terminals in plated apertures provided in a substrate is also disclosed, wherein the solder bands are applied to the terminals according to the above mentioned application technique. A technique of flattening the solder bands, and the resulting terminal structures having flattened solder bands adhered thereto are also disclosed. Flattening of the solder bands facilitates insertion of the banded terminals into the plated apertures by changing the shape of the solder bands and by reducing their structural integrity through the creation of numerous hairline fractures.