Abstract: A wireless communication device and system is provided for detecting an incoming wireless signal and selecting the power state and performance of one or more interface units that are adapted to receive the wireless signal. Depending on which interface unit recognizes the incoming signal, that unit may be supplied full power and maximum performance, whereas all other interface units are powered down or placed in a lower performance state. User preferences can be input into the device and used to manually select certain interfaces. The user preferences can be overridden by the automatic detection mechanism or vice-versa. The detection and user preferences are affected by the network characteristics, and the location, traffic, and interrogation/acknowledge signals sent across the network in order to optimize the automatic selection and user preference capability.

Abstract: A palette for a pen tablet computer that facilitates secure gripping of the computer by the user and operation thereof. One edge of the palette includes a palm swell on one side, function buttons on the opposing side, and a thumb hole extending between the two sides. A support arm engagement region extends from the one edge diagonally to the opposite, parallel edge. In one form, the computer can be selectively attached and detached from the palette.

Abstract: An optical transmission system in a computer tomograph for transmitting modulated optical signals between a first unit and a second unit, the first unit being supported to be rotatable relative to the second unit, comprises: a light guide disposed along a circular or annular track on the first unit; at least one first light coupler connected with the light guide for coupling light into or out of the light guide; at least one second light coupler disposed on the second unit to be movable relative to the light guide for coupling light into or out of the light guide. In order to remove from the light guide surface any contaminating matter that would lead to a high signal attenuation or an interference with transmission, a cleaning unit is provided for removing dirt and dust particles. Furthermore, a sealing of the system is provided by applying, amongst other means, pressurized air or electrostatic filtering.

Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer.

Abstract: A system and method are provided for built-in-self test of any bits that have slipped from their appropriate positions within a frame character clock cycle. If a bit has slipped, then the built-in-self test mechanism can also implement either a clock generation stretch operation or a barrel shift operation to readjust the frame boundary output from a receiver with a 1-to-N deserializer. A pseudo-random bit sequence can be generated having the same logic value in both the receiver and transmitter, where the output of the deserializer which receives the transmitted bits is compared bit-by-bit with the receiver-generated bits as part of the built-in-self test mechanism. If a bit is determined to have been slipped, then error correction occurs with aliasing and phase jitter in mind.

Abstract: An improved clock recovery system, phase-locked loop, and phase detector are provided as well as a method for generating charge pump signals. The clock recovery system includes a phase-locked loop. The phase-locked loop includes a phase detector and a voltage-controlled oscillator. The phase detector generates pump signals that change linearly with respect to differences between phases of an incoming signal and a clocking signal. The oscillator is coupled to receive the pump signals and produce a clocking signal at a frequency not exceeding the frequency of the incoming signal. For example, the oscillator can produce clocking signals at one-half the frequency of the incoming signal, where the incoming signal is preferably a maximum bit rate of a data signal from which the clock signal is recovered. The phase detector can include a first flip-flop and second flip-flop.

Abstract: Disclosed herein is a current sense amplifier (ISA) circuit with increased speed, less insensitivities to process variation, better stability and improved output signal swing. According to one embodiment, the ISA circuit described herein may include a pair of output nodes and a first pair of load transistors, each coupled between a different one of the output nodes and ground for pulling the output nodes down to a first voltage value at the beginning of a sense cycle. In addition, a pulse generation circuit is included for activating the first pair of load transistors at the beginning of the sense cycle and deactivating the first pair of load transistors once the first voltage is reached. When activated, the first pair of load transistors provide a relatively low resistance current path between the output nodes and ground. This decreases the output node discharge time and increases the overall speed of the sense amp without compromising circuit stability and output swing.

Abstract: An architecture for an improved non-volatile memory device supporting multiple memory interface options is disclosed herein. In one embodiment, the improved memory device includes a magnetic random access memory (MRAM) array and at least one memory interface block, which is configured for accessing a different type of memory array other than the MRAM array. A smart MRAM interface block is also included and coupled between the plurality of memory interface blocks and the MRAM array. The smart MRAM array is configured for accessing the MRAM array using commands intended for the MRAM array, as well as commands intended for the different type of memory array. A method for operating the improved non-volatile memory device is also disclosed herein.

Abstract: A low voltage, high-gain current/voltage sense amplifier (ISA/VSA) circuit with improved read access time is provided herein. According to one embodiment, the ISA/VSA described herein includes a pair of current reference branches for generating a pair of reference currents in response to a pair of differential input signals supplied thereto. The differential input signals are differential voltages which are converted to differential currents by the current reference branches. In some cases, the current reference branches may be used for amplifying and mirroring the reference currents onto output nodes of the ISA/VSA. In doing so, the current reference branches may increase the amplification and improve the performance of the sense amp circuit, even under extreme mismatch conditions. In addition, positive feedback may be used within the ISA/VSA design to further increase the amplification and speed of the sense operation.

Abstract: A frequency synthesizer is provided having a fractional-N control circuit and method. The control circuit can operate as having a modulator that selectively applies any fractional ratio to a frequency divider within, for example, a feedback loop of a PLL. The modulator can be a delta-sigma modulator or any sequential state machine that can be implemented as the control circuit, and can select amongst a plurality of vector values. The vector values can be spaced relatively close to each other, and the incoming present vector values can each be added to a value chosen from the immediately preceding set of potential values. The selector circuit chooses from among the present set of vector values depending on whether the sum is nearest a target value. The sum nearest the target value is, therefore, selected as the present vector value, and the process is repeated in time for each vector value having a corresponding P value to form a pattern of P values sent to the divider of the PLL.

Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

Abstract: Methods and systems are provided which are adapted to process a microelectronic topography, particularly in association with an electroless deposition process. In general, the methods may include loading the topography into a chamber, closing the chamber to form an enclosed area, and supplying fluids to the enclosed area. In some embodiments, the fluids may fill the enclosed area. In addition or alternatively, a second enclosed area may be formed about the topography. As such, the provided system may be adapted to form different enclosed areas about a substrate holder. In some cases, the method may include agitating a solution to minimize the accumulation of bubbles upon a wafer during an electroless deposition process. As such, the system provided herein may include a means for agitating a solution in some embodiments. Such a means for agitation may be distinct from the inlet/s used to supply the solution to the chamber.

Abstract: A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.

Abstract: A low-loss, high-efficiency, broadband antenna including both electric and magnetic dipole radiators is provided herein. The broadband antenna may be referred to as a “P×M antenna” and may generally include a ground plane; a magnetic radiator formed within the ground plane; a conductive feed arranged within a first plane, which is parallel to the ground plane; and an electric radiator arranged within a second plane, which is perpendicular to the ground plane and coupled at one end to the conductive feed. According to a particular aspect of the invention, the electric and magnetic radiators are substantially complementary to one another and are coupled for producing a P×M radiation pattern over a broad range of operating frequencies. One advantage of the P×M antenna described herein is that the complementary antenna elements are combined without the use of a lossy, resistive matching network, thereby increasing the efficiency with which the P×M radiation pattern is produced.

Abstract: The present invention relates to improved covalent coupling of two or more entities such as biomolecules, polymer compositions, organic/inorganic molecules/materials, and the like, including their combinations, through one or more novel reactive groups attached to linker groups of 2-1000 atoms length. The present invention also contemplates the use of bifunctional bridge molecules to link two or more entities, wherein the functional groups of the bridge molecules are the novel reactive groups of the present invention.

Abstract: A device for receiving digital signals comprising at least one receiving antenna, a measuring means for determining parameters of relevance to signal quality, a digitizer, and a signal-processing unit. The signal-processing unit is controlled to optimize the reception of the digital signals on the basis of the parameters determined by the measuring means. A signal-processing unit processes signals from the receiving antenna and a digitizer converts the processed signals so that the converted processed signals can be measured to determine their relevance signal quality; a transmitter conductor array coupled to the receiving unit can be controlled therefrom. Controlling the signal quality occurs using a dielectric or ferromagnetic materials, impedance elements, or actuators between the receiving antenna and the transmitter conductor array.

Abstract: An improved Content Addressable Memory (CAM) architecture and method for operating the same is provided herein. The improved CAM architecture may generally include an array of memory cells arranged into rows and columns, where each row includes a number of memory cells configured for storing one word. In particular, the number of memory cells may be coupled to a plurality of local match lines which, when combined through a hierarchy of two or more logic gates, form a match line signal for the entire word. Dynamic logic is used within a compare portion of each memory cell to reduce the occurrence of functional failures. In addition, the improved method for operating the CAM reduces power consumption and peak current, and improves timing, by eliminating the need to restore the match line voltage to a preset voltage level before each new compare operation.

Abstract: A slide track mounting or a contact brush mounting for a sliding contact assembly comprises insulators having a surface structure that is a combined microstructure and nanostructure. Thereby an accumulation of dirt and abraded particles from contact brushes on the insulators is substantially reduced. This allows creep paths to be shortened and periods between maintenance operations for cleaning to be prolonged.

Abstract: Memory circuits having different configurations of local word line driving circuits (LWLDC) and methods for designing such circuits are provided. The memory circuits include an array of memory cells and a plurality of local word lines each coupled to a different subset of the array of memory cells. The memory circuit further includes a plurality of LWLDC respectively coupled to the plurality of local word lines, a global word line bus coupled to the plurality of LWLDC, and a global word line driving circuit (GWLDC) coupled to the global word line bus. At least one of the plurality of LWLDC may be configured to have a smaller amount of load capacitance than another LWLDC arranged comparatively farther from the GWLDC. In some embodiments, the variance of load capacitance may be induced by a variance of size among the plurality of LWLDC, specifically with reference to different transistor width dimensions.

Abstract: A device for transmitting modulated optical signals between a first unit and a second unit, in which the first unit is supported to be rotatable relative to the second unit, comprises a light guide along a circular track on the first unit, a first light coupler for coupling light into or out of the light guide, and a second light coupler disposed on the second unit and movable relative to the light guide, for coupling light into or out of the light guide. A coupling of light into the light guide is effected by means of a beam splitters and a light deflecting means.