Abstract: An operational amplifier includes a pair of differentially coupled PNP transistors driving a current mirror circuit. The base of the each of the transistors is coupled to the source of a JFET follower transistor each of which in turn has a gate coupled to one of the amplifier's inputs. First and second current sources are coupled to the source electrodes of each of the JFETs for the purpose of supplying a current thereto equal to that JFET's I.sub.DSS (its drain current when its gate and source are shorted).

Abstract: A CMOS memory cell is provided having separate read and write bit lines and coupling devices associated therewith which provide improved read and write times for the cell. The separate read line is coupled to the cell via a bipolar transistor which supplies increased drive current to the read bit line thereby decreasing the read time. The separate write line is coupled to the cell via a low impedance diode which reduces the write time.

Abstract: A request with response mechanism and method for a local area network controller utilizes an enable bit, a pointer, a counter and an interrupt to create the proper response to a received request with response data frame without the active aid of a host computer.

Abstract: A circuit and method for demodulation of transmitted phase-coherent signals including recovery of the clock and data signals associated therewith. A clock recovery circuit detects a zero crossing of the transmitted signal which occurs every one-half period of the lowest frequency transmitted signal. A data recovery circuit detects the presence or absence of a zero crossing during a window portion of each one-half period of the lowest frequency transmitted signal.

Abstract: A voltage translator circuit is provided to reduce a supply voltage to a lower, predetermined, relatively constant and unconditionally stable operating voltage without the use of external components. A voltage divider comprising a plurality of series connected CMOS FETs located in P-regions, is used to establish an operating voltage. Additional CMOS FETs are used to supply the load current and control the no-load voltage.

Abstract: A system and method for altering an aspect of one of a plurality of coincident visual objects comprises means for generating first and second coincident visual objects, the first visual object having an alteration attribute thereof. Means are provided for identifying the alteration attribute of the first visual object in conjunction with means responsive to the identifying means for altering the aspect of the second visual object. In accordance with the system and method of the invention, the color of a true object overlapping a fixed object of lesser priority may be modified such that it appears that the true object has entered the shadow of the fixed object.

Abstract: A video raster display system having a dedicated display address generator is provided. In addition to a microprocessor contained within the video display system providing addresses to a memory the display address generator also generates addresses. The display address generator has a logic unit having a first and a second bus as inputs. A first plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives inputs from the microprocessor. A second plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives inputs from a video data generator. A third plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives the output from the logic unit to controllably provide this output to the logic unit for subsequent operations.

Abstract: A video field decoder is provided in a raster scan interlaced video display system, which decoder provides an indication of whether the odd or even field is currently being displayed. The decoder circuit compares the horizontal and vertical sync signals and provides an output on their coincidence, indicating a given field level (odd or even) is being displayed.

Abstract: An overvoltage protection circuit for directing a surge current on an input/output line, in particular, a telephone line, to a ground terminal when the surge current exceeds a predetermined level.

Abstract: A serial communications interface for coupling a physical layer such as a modem to a media access control layer in a token bus network provides data and station management information therebetween on a plurality of bidirectional data lines providing management functions and a unique serial bus for control transfer in addition to communications data.

Abstract: An MOS SCR and MOSFET "H" switch circuit for a DC motor is provided which allows for the use of a supply voltage of greater than 20 volts by clamping the gate-to-cathode voltage of the SCR's used therein to a predetermined value which is less than the gate-to-cathode breakdown voltage of said SCR's.

Abstract: A true object generation system for true object generation in a video display generator or video display generator which comprises means for storage of data representative of an object run length and pel value and means responsive to the object run length data for holding the pel value at the storage means output for a time proportional to the object run length. True objects may be generated by either a run length or bit mapped code structure.

Abstract: A video display system is provided having a programmable video display generator. The video display generator is divided into a control unit and an interface unit. The control unit has a dedicated display address generator which frees up the microprocessor used in the video display system. The system is capable of operation with several different microprocessors as well as with different types of random access memories. Circuitry within the interface unit advises the system of the type of microprocessor being used as well as the type of random access memory. The interface unit controls character generation as well as final attribute circuitry which gives the video display generator a high degree of capability while minimizing the amount of circuitry required.

Abstract: A universal vertical countdown and method for a video display is provided which will handle all standard vertical signals and systems while giving the same noise performance as a self-locking system. Control of the resetting of the countdown during the acquisition phase enables the use of a single set of storage elements to provide all major decodes necessary for the system.

Abstract: A safe operating area circuit in combination with a current sensing circuit is coupled to an input voltage line and has a control line input in which the combination provides a current limited output on an output voltage line in response thereto. Break-points may be selectably established in the current limit curve for the output switching device by means coupling the input and output voltage lines.

Abstract: A PWM controller for an electrical utilizes a dual differential input topology comprising two input comparators deriving a proportional reference from two potentiometers for providing a variable pulse width modulated output. The pulse width modulation controller of the present invention does not require scaling and may be utilized in appliances, robotics, toys and in conjunction with other electromechanical and electrical loads.

Abstract: A compensation circuit for stabilization of a circuit node coupled to an integrated circuit substrate by a parasitic capacitance of a value C.sub.1 has a displacement current substantially equal to C.sub.1 dv/dt. A switching device having a gain beta can either supply a current to, or draw a current from, the circuit node substantially equal to C.sub.2 .beta. dv/dt which is greater than the displacement current thereby obviating oscillation of an integrated circuit output due to capacitive coupling of the substrate to sensitive circuit nodes.

Abstract: An integrated circuit and method for biasing an impurity region, in particular an epitaxial layer, to a level substantially equal to a supply voltage level yet exhibiting a high reverse breakdown voltage to negative transients of the supply voltage. The integrated circuit and method is of especial utility in power BIMOS and other applications having the substrate at or near the supply voltage level.

Abstract: A microcomputer controlled monitoring system and method for detecting an electrical open, shorted or operative condition of an electrical load. A load switch circuit couples the load to a common voltage line and is controlled by a single drive line from a microcomputer controlled load monitor circuit.

Abstract: A frequency generator in which the PLL frequency synthesizer and the VCO are directly modulated by an input serial data stream for providing an FSK modulated RF output signal useful in narrowband data communication systems. The serial data stream may alternatively modulate either the PLL frequency synthesizer or the VCO alone.