Abstract: A memory map for a computer system is configurable. For example a first section of the memory map (e.g., the lower address space) is configurable so that when the process accesses this section, different devices will respond depending on the memory map in effect. In one embodiment, external non-volatile memory is accessed during a first time period based on a reset memory map. After initialization, the memory may is changed to a normal one so that subsequent accesses to the same section of the memory map result in accesses to faster memory (e.g., internal SRAM). In the case where the reset vector and interrupt vectors have relatively close addresses, the configurability of the memory map allows the reset vector to be handled through accesses to non-volatile memory while interrupt vectors are handled through accesses to faster internal SRAM.

Abstract: A disc storage system servo code detector is disclosed that provides enhanced error correction capabilities during both tracking and seeking by increasing a minimum distance dmin between valid codewords and by increasing a minimum distance {circumflex over ( )}dmin from the signal space between adjacent codewords to the decision boundaries of all other valid codewords. The signal space with respect to the minimum distances is not a limiting aspect of the invention; however, in the preferred embodiment the codewords are selected to maximize the minimum distances in Euclidean space. Thus, the read signal is sampled and equalized according to a partial response spectrum, and maximum likelihood detection is employed to detect the servo codewords in Euclidean space. The code rate is selected according to certain design criteria such as the amount of error correction desired, the data density, and the cost and complexity of the encoder/decoder circuitry.

Abstract: Logic for a 1394-enabled system is disclosed which enables multiple internal link layers, connected to corresponding 1394 devices, to communicate with each other without an intervening physical layer, thereby eliminating one or more PHY chips and associated PHY-PHY cables and connectors (reducing both cost and power consumption). Using a single, optional PHY chip or the integrated PHY block, the internal devices can also communicate with external 1394 devices. The logic can also include, among other elements: multi-node logic to permit data to be transmitted between a device on an external 1394 bus and a selected one of two or more internal link layers; packet overlap logic to permit data to be transmitted between two internal link layers while data is being transmitted on an external 1394 bus; and a PHY-emulation module to provide each internal link layer with a corresponding “virtual” PHY layer having a node ID which is unique on an external 1394 bus.

Abstract: A method and apparatus for calibrating the components of a Partial Response Read Channel (PRML) integrated circuit utilized in a magnetic storage device including a channel quality circuit, incorporated within the read channel IC, for automatically measuring the performance of each component as data is read by the channel. An error measurement for each component is generated as an indicator of the component's performance, such as a sample error generated by measuring the difference between the samples read by the channel and expected samples. The read channel components are programmed over a range of settings to determine the settings that generate the minimum error. By programming the components with settings corresponding to minimum error rates, the read channel is optimized.

Abstract: The invention includes disk drive circuitry, systems, and methods. The disk drive system comprises control circuitry and a disk device. The disk device stores data and transfers an analog signal representing the data. The control circuitry receives the analog signal, converts the analog signal into a digital signal, transfers the digital signal, and biases an error signal. The control circuitry includes an analog-to-digital converter, adaptive filter, a decoder, and error signal circuitry. The analog-to-digital converter receives and samples the analog signal to generate a sampled signal. The adaptive filter shapes the sampled signal based on coefficients to produce a shaped signal. The decoder decodes the shaped signal to generate the digital signal. The error signal circuitry generates the biased error signal to adjust the coefficients in the adaptive filter.

Abstract: A sampled amplitude read channel is disclosed for disc storage systems that extracts early-decisions from a discrete-time trellis sequence detector to generate estimated target values for use in decision-directed timing recovery, gain control, and adaptive equalization. The trellis sequence detector comprises a metric generator for generating error metrics corresponding to a plurality of states of a state transition diagram, and a plurality of path memories which correspond to the paths of a trellis. The path memories store a plurality of survivor sequences which eventually merge into a most likely sequence at the output of the path memories. To reduce the latency in generating the estimated target samples, the trellis sequence detector outputs an early-decision from an intermediate location within the path memories. The early-decision is then converted into the partial response signaling space of the read signal samples.

Abstract: A discrete-time sliding mode controller (SMC) controls the motion of mechanical apparatus such as a read head in a disk storage system. The overall control effort is generated by combining a linear control effort with a discrete-time sliding mode control effort generated by switching between gains in order to drive the system's phase states toward a sliding line trajectory. An estimate of a reference is generated and added to the control effort, thereby providing an approximation of the derivative of the reference signal. Estimating the reference signal may be performed by various methods, depending on whether the reference is known, unknown but repeatable, or completely unknown and non-repeatable. A least-mean-square (LMS) algorithm is employed to estimate the reference signal by computing coefficients of a function which minimizes a particular system parameter.

Abstract: A sampled amplitude read channel for use in disk storage systems (magnetic or optical) is disclosed comprising a simplified branch metric calculator for use in a trellis sequence detector. Instead of computing the traditional Euclidean branch metric as the squared difference between the actual signal sample and the expected signal sample of the target partial response, the present invention computes a simplified branch metric which is then saturated in order to reduce the number of bits required to calculate and store the branch metrics, thereby simplifying the branch metric calculators as well as reducing the add-compare-select (ACS) circuitry for each state in the trellis. Furthermore, the saturation technique of the present invention is substantially data independent meaning that the saturation threshold is essentially independent from the signal samples used to compute the branch metric.

Abstract: Analog modulator circuitry 401 includes an integrator 707. First switched capacitor circuitry 710, 711, 713, 714 selectively samples a first amount of charge from a feedback signal and couples that first amount of charge to the first and second inputs of the integrator. Second switched capacitor circuitry 711, 714, 716, 717 selectively samples a second amount of charge from the feedback signal and couples that second amount of charge to the first and second inputs of the integrator stage to selectively compensate for an offset of an input signal to the integrator with respect to a reference voltage.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems comprising an MEEPR4 equalizer, an MEEPR4 sequence detector matched to an RLL d=1 constraint, and an encoder/decoder for implementing a channel code that codes out (2,4,2) quasi-catastrophic data sequences. A rate n/m finite state encoder encodes n bits of user data into m bits of write data, and a sliding block decoder decodes m bits of read data into n bits of estimated user data. The encoder uses the current n bits of user data as well as a current state of a state machine to generate the m bits of write data, where a state-splitting technique is employed to achieve a high code rate in a practical, cost effective implementation. The decoder decodes the m bits of read data into the n bits of estimated user data by evaluating the current detected codeword in context with the following detected codeword.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems comprising a encoder/decoder for implementing a high rate channel code that codes out specific minimum distance error events of a trellis sequence detector by enforcing a particular code constraint. The trellis sequence detector comprises a state machine matched to the code constraint which effectively removes the corresponding minimum distance errors from the detected output sequence. Additionally, the channel code encodes redundancy bits into the write data for implementing an error detection code. The redundancy bits are processed during a read operation to generate an error syndrome used to detect and correct other dominant error events, such as the NRZ (+) and (+−+) error events. In this manner, the most likely error events of the trellis sequence detector are either coded out by the channel code constraint, or detected and corrected using the error syndrome.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems (e.g., magnetic or optical) comprising a sampling device for sampling the analog read signal emanating from the read head positioned over a disk storage medium, a channel equalizer for equalizing the signal samples according to a desired partial response, a trellis sequence detector for detecting a preliminary sequence from the equalized signal samples, and a post processor for correcting errors in the preliminary sequence, including errors caused by the channel equalizers correlating the noise in the read signal. The preliminary sequence detected by the sequence detector is remodulated into ideal partial response samples and then subtracted from the actual signal samples to generate a sequence of sample errors. The sample errors are then filtered by a sample error filter, and the filtered sample errors are correlated with error event sequences corresponding to the most likely error events of the trellis sequence detector.

Abstract: An adaptive, discrete-time sliding mode controller (SMC) is disclosed which detects and adapts to gain variations in the controlled plant. The overall control effort is generated by combining a linear control effort with a discrete-time sliding mode control effort generated by switching between gains in order to drive the system's phase states toward a sliding line trajectory. A sliding mode variable &sgr;k defines the position of the system phase states relative to the sliding line. The SMC controller is designed such that the sliding mode variable &sgr;k crosses the sliding line and changes sign at every sample interval. For the nominal plant gain, the SMC controller is also designed such that the magnitude of the sliding mode variable &sgr;k+1=−&sgr;k will remain constant (&sgr;k+1=−&sgr;k) and substantially constrained to |&sgr;k|=&Dgr;/(1+&lgr;) where &Dgr; and &lgr; are predetermined design constants.

Abstract: A discrete time servo demodulation technique incorporated within a sampled amplitude read channel to demodulate embedded servo field information stored on a magnetic medium. The servo field information is transduced by a read head into an analog signal, and converted to a sequence of sample values in the read channel. The demodulation technique is responsive to the sample values and includes a discrete time peak detector for detecting servo data, and a discrete time servo burst amplitude detector for measuring the amplitude of servo bursts. Peaks are detected in the analog read signal by sensing a change of slope from the sequence of sample values. The peaks are qualified by polarity in that a peak is detected only if its polarity is opposite in sign from the previous peak. The servo burst amplitudes are measured by interpolating, rectifying, and accumulating the sequence of sample values corresponding to the servo bursts.

Abstract: A quadrature signal generator for optical disk storage devices is disclosed comprising a differential phase detector (DPD) implemented as an adaptive length dual arm correlator. A photo diode generates a light beam for irradiating the optical disk during read operations, and a pair of diagonal signals S1 and S2 are generated by adding a pair of respective quadrants of a four-quadrant photodetector which detects the light beam reflected from the disk. The phase offset between the diagonal signals represents the centerline offset of the light beam from the centerline of a data track recorded on the optical disk. A first and second position error signals (PES) are generated by computing the difference and sum between a positive and negative correlation of the diagonal signals S1 and S2, otherwise referred to as a dual arm correlation (DAC) ##EQU1## where .DELTA. is the correlation offset and L is the correlation length.

Abstract: An H configuration write driver circuit is provided which includes integral fault detection circuitry. A load device, such as a magnetic tape recorder write head, is coupled in an H configuration with four drive transistors. A first and second drive transistor are coupled to opposite ends of the load device and produce current flow through the load device in a first direction. A third and fourth drive transistor are coupled to opposite ends of the load device to produce current flow through the load device in the opposite direction. A resistor is coupled in series between each drive transistor and the load device and these resistors serve to determine the time constant of the rise/fall of current through the inductive write head and to limit current flow through a drive transistor in the event of a short circuit condition therein.

Abstract: A multi-layered error detection and correction (EDAC) system is disclosed for processing an error correction code (ECC) typically employed in optical disk storage devices. A first layer of the EDAC system includes a primary ECC, such as a multiple burst Reed-Solomon code, and a second layer incudes a secondary ECC, such as a CRC code, for use in verifying the validity of the corrections made using the primary ECC. The primary ECC is multi-dimensional and, in the embodiment disclosed herein, it is a two-dimensional P/Q product code typically employed in a CD-ROM storage device. The secondary ECC operates in unison with the primary ECC. As the EDAC system processes and corrects the data using the primary ECC, the EDAC system also simultaneously updates the secondary ECC. In this manner, when the EDAC system is finished processing the data using the primary ECC, the validation syndrome generated by the secondary ECC is available immediately for checking the validity of the corrections.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.

Abstract: An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM.sub.0 -REM.sub.3. The check remainder bytes REM.sub.0 -REM.sub.3 are utilized to generates syndromes S.sub.1, S.sub.3 and a factor S.sub.B, the syndromes in turn being used to obtain either one or two error location positions (.alpha..sup.L1, .alpha..sup.L2). The mathematical calculation circuit (104) not only generates the syndromes S.sub.1, S.sub.3 and factor S.sub.B, as well as the error location positions (.alpha..sup.L1, .alpha..

Abstract: A disk storage system is disclosed wherein user data received from a host system is first encoded according to a first channel code having a high code rate, and then encoded according to an ECC code, such as a Reed-Solomon code, wherein the ECC redundancy symbols are encoded according to a second channel code having low error propagation. In the preferred embodiment, the first channel code is a RLL (d,k) code having a long k constraint which allows for longer block lengths (and higher code rates). During read back, a synchronous read channel samples the analog read signal a synchronously and interpolates the asynchronous sample values to generate sample values substantially synchronized to the baud rate. In contrast to conventional synchronous-sampling timing recovery, interpolated timing recovery can tolerate a longer RLL k constraint because it is less sensitive to noise in the read signal and not affected by process variations in fabrication.