Abstract: A discrete-time sliding mode controller (SMC) controls the motion of a read head actuated over a disk storage medium during tracking operations. The discret-time SMC comprises a linear signal generator for generating a linear control signal, and a sliding mode generator for generating a sliding mode signal. These signals are combined and applied to a voice coil motor (VCM) for positioning the read head over a particular data track recorded on the disk. The linear signal generator and the gain (c&Ggr;)−1&Dgr; are designed such that once the sliding mode variable &sgr;k crosses the sliding line the first time, it will cross the sliding line in every successive sample period resulting in a zigzag motion about the sliding line wherein &sgr;k changes sign at every sample period. The switching action and resulting chatter of the sliding mode controller are minimized by adjusting the width of the boundary layer through appropriate selection of predetermined constants &Dgr; and &lgr;.

Abstract: In a sampled amplitude read channel for disk storage systems, a post processor is employed to correct errors in a preliminary sequence caused by the dominant error events of a trellis sequence detector. By correlating a sample error sequence with the dominant error events, error filters compute a Euclidean distance error metric between the samples sequence selected by the trellis sequence detector and the sample sequence that would have been selected if an error event did not occur. The minimum error metric is assigned to the symbols in the preliminary sequence that differ from the symbol sequence that would have been generated if the error event did not occur. After processing a predetermined number of the symbols in the preliminary sequence, the error metrics assigned, to the symbols are used to detect and correct error events in the preliminary sequence.

Abstract: An auto-calibrating companion bit successive approximation system uses sampling and balancing capacitors in a charge redistribution digital-to-analog converter having multi-valued capacitors of magnitudes enabling redundant expression of electric charge values. Companion bits are used with sets of balancing capacitors for successive approximation of sampling voltages. A charge redistribution digital-to-analog converter has a sampling and balancing capacitors including associated companion bit capacitors represented by digital weights which are saved in memory. A non-binary weighted set of capacitors provides redundancy in a charge redistribution digital-to-analog converter employed in a successive approximation register architecture.

Abstract: A technique for correcting higher order delta sigma modulators in audio components, which use mutually nonlinear feedback and feed forward functions. Methods and apparatus are provided to correct jitter and spread in the delta sigma converter due to quantization error, to permit the processing of data streams entering the converter at a different clock rate from that of the modulator, and to permit step up ratios to be changed on the fly in order to reduce radio frequency interference from the output signal.

Abstract: A system and method is disclosed for calibrating comparators of an ADC while the ADC continues to operate in an uninterrupted fashion. Groups (banks) of interleaved comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra “proxy” or replacement comparators. More particularly, at periodic intervals the comparators of one bank may be disconnected from the standard ADC circuitry for calibration or auto-zeroing while the comparators in the remaining bank(s) are left in the data conversion path. In order to prevent a significant degradation in the conversion quality, logic downstream of the comparators provides the necessary adjustments to accommodate for the removal of the comparators and outputs a word of the desired bit length. The multi-bank ADC is particularly advantageous for use with optical data storage systems.

Abstract: A sampled amplitude read channel is disclosed for magnetic disk storage systems utilizing a read head exhibiting a non-linear response such as a magneto-resistive (MR) read head. A sensor of the read head is adjusted to operate in a region of its response that provides optimum gain even though it may be a region of higher non-linearity. To compensate for the non-linearity introduced into the read signal, the read channel further comprises an adaptive non-linear correction circuit that is adaptively tuned by a least-mean-square (LMS) adaptation circuit. The analog read signal is sampled and the discrete time samples equalized into a desired partial response prior to sequence detection. The non-linear correction circuit is inserted into the read path prior to the sequence detector in order to attenuate the non-linear distortions that would otherwise degrade the performance of the sequence detector.

Abstract: The present invention correlates noise from a delta sigma modulator with noise from the same modulator passed through a nonlinear block whose purpose is to isolate the imperfection being measured. Once the imperfection is measured the results may be used to correct the output of the delta sigma modulator, to accept or reject chips or for other purposes.

Abstract: Circuitry is provided to compensate for distortion introduced into the output signal of a delta sigma digital to analog converter (DAC) by the power output stage of the amplifier. Such distortion is not consistent for a given output data value or short series of data values, but must be either measured and corrected in real time or must be corrected in real time based upon a sophisticated model of the system that predicts the distortion. Correction is applied to one or more feedback loops in the delta sigma converter. Distortion caused by fluctuations in the power supply voltage may also be modeled and corrected in real time.

Abstract: An improved read channel for storage and communication application particularly useful in optical storage applications. The improved read channel includes a Viterbi sequence detector tuned to a preferred partial response target well suited to sensing of pulses in the waveforms typical of optical storage read heads. In particular, the read channel of the present invention implements pulse and sequence detection for a partial response target having a spectral null at the Nyquist frequency and having a relative minimum between zero and the Nyquist frequency. In other words, the partial response target of the improved read channel is not a monotonic decreasing function between zero and the Nyquist frequency as is known in present read channels. More specifically, in the preferred embodiment, the partial response target of the read channel includes a spectral null at the Nyquist frequency and another spectral null at half the Nyquist frequency.

Abstract: A multibit data converter has an output parallel unit element converter fed by a multibit signal, and noise shaping dynamic element matching (DEM) apparatus for selectively activating units in the converter. The DEM apparatus includes a plurality of noise shaping components. Each components has as an input one signal to the converter, and each includes a first integrator having as its input the input to the component, and a second integrator having as its input the output of the first integrator, and forms one or more component outputs. A signal in the second integrator is clipped. A vector quantizer orders the component outputs and activates converter elements according to the ordering.

Abstract: Distortion and noise in high power digital PWM amplifiers is reduced by measuring the difference between the desired output signal and the actual output signal on a pulse by pulse basis. This analog error is converted into a digital signal with an analog to digital converter (ADC). The digital error signal is then used to correct the feedback of the delta sigma modulator in real time. Preferably, more than one moment of the modulator signal is corrected via the feedback. Preferably, the predictable error of the circuitry which is known a priori is also corrected by correcting the delta sigma modulator feedback. A specialized ADC allows the loop delay to be low, without compromising accuracy.