Abstract: A sampled amplitude read channel is disclosed for disc storage systems that extracts early-decisions from a discrete-time trellis sequence detector to generate estimated target values for use in decision-directed timing recovery, gain control, and adaptive equalization. The trellis sequence detector comprises a metric generator for generating error metrics corresponding to a plurality of states of a state transition diagram, and a plurality of path memories which correspond to the paths of a trellis. The path memories store a plurality of survivor sequences which eventually merge into a most likely sequence at the output of the path memories. To reduce the latency in generating the estimated target samples, the trellis sequence detector outputs an early-decision from an intermediate location within the path memories. The early-decision is then converted into the partial response signaling space of the read signal samples.

Abstract: A discrete-time sliding mode controller (SMC) controls the motion of mechanical apparatus such as a read head in a disk storage system. The overall control effort is generated by combining a linear control effort with a discrete-time sliding mode control effort generated by switching between gains in order to drive the system's phase states toward a sliding line trajectory. An estimate of a reference is generated and added to the control effort, thereby providing an approximation of the derivative of the reference signal. Estimating the reference signal may be performed by various methods, depending on whether the reference is known, unknown but repeatable, or completely unknown and non-repeatable. A least-mean-square (LMS) algorithm is employed to estimate the reference signal by computing coefficients of a function which minimizes a particular system parameter.

Abstract: A sampled amplitude read channel for use in disk storage systems (magnetic or optical) is disclosed comprising a simplified branch metric calculator for use in a trellis sequence detector. Instead of computing the traditional Euclidean branch metric as the squared difference between the actual signal sample and the expected signal sample of the target partial response, the present invention computes a simplified branch metric which is then saturated in order to reduce the number of bits required to calculate and store the branch metrics, thereby simplifying the branch metric calculators as well as reducing the add-compare-select (ACS) circuitry for each state in the trellis. Furthermore, the saturation technique of the present invention is substantially data independent meaning that the saturation threshold is essentially independent from the signal samples used to compute the branch metric.

Abstract: A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.

Abstract: Analog modulator circuitry 401 includes an integrator 707. First switched capacitor circuitry 710, 711, 713, 714 selectively samples a first amount of charge from a feedback signal and couples that first amount of charge to the first and second inputs of the integrator. Second switched capacitor circuitry 711, 714, 716, 717 selectively samples a second amount of charge from the feedback signal and couples that second amount of charge to the first and second inputs of the integrator stage to selectively compensate for an offset of an input signal to the integrator with respect to a reference voltage.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems comprising an MEEPR4 equalizer, an MEEPR4 sequence detector matched to an RLL d=1 constraint, and an encoder/decoder for implementing a channel code that codes out (2,4,2) quasi-catastrophic data sequences. A rate n/m finite state encoder encodes n bits of user data into m bits of write data, and a sliding block decoder decodes m bits of read data into n bits of estimated user data. The encoder uses the current n bits of user data as well as a current state of a state machine to generate the m bits of write data, where a state-splitting technique is employed to achieve a high code rate in a practical, cost effective implementation. The decoder decodes the m bits of read data into the n bits of estimated user data by evaluating the current detected codeword in context with the following detected codeword.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems comprising a encoder/decoder for implementing a high rate channel code that codes out specific minimum distance error events of a trellis sequence detector by enforcing a particular code constraint. The trellis sequence detector comprises a state machine matched to the code constraint which effectively removes the corresponding minimum distance errors from the detected output sequence. Additionally, the channel code encodes redundancy bits into the write data for implementing an error detection code. The redundancy bits are processed during a read operation to generate an error syndrome used to detect and correct other dominant error events, such as the NRZ (+) and (+−+) error events. In this manner, the most likely error events of the trellis sequence detector are either coded out by the channel code constraint, or detected and corrected using the error syndrome.

Abstract: An adaptive, discrete-time sliding mode controller (SMC) is disclosed which detects and adapts to gain variations in the controlled plant. The overall control effort is generated by combining a linear control effort with a discrete-time sliding mode control effort generated by switching between gains in order to drive the system's phase states toward a sliding line trajectory. A sliding mode variable &sgr;k defines the position of the system phase states relative to the sliding line. The SMC controller is designed such that the sliding mode variable &sgr;k crosses the sliding line and changes sign at every sample interval. For the nominal plant gain, the SMC controller is also designed such that the magnitude of the sliding mode variable &sgr;k+1=−&sgr;k will remain constant (&sgr;k+1=−&sgr;k) and substantially constrained to |&sgr;k|=&Dgr;/(1+&lgr;) where &Dgr; and &lgr; are predetermined design constants.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems (e.g., magnetic or optical) comprising a sampling device for sampling the analog read signal emanating from the read head positioned over a disk storage medium, a channel equalizer for equalizing the signal samples according to a desired partial response, a trellis sequence detector for detecting a preliminary sequence from the equalized signal samples, and a post processor for correcting errors in the preliminary sequence, including errors caused by the channel equalizers correlating the noise in the read signal. The preliminary sequence detected by the sequence detector is remodulated into ideal partial response samples and then subtracted from the actual signal samples to generate a sequence of sample errors. The sample errors are then filtered by a sample error filter, and the filtered sample errors are correlated with error event sequences corresponding to the most likely error events of the trellis sequence detector.

Abstract: A sampled amplitude read channel for optical disk storage systems is disclosed comprising an all digital timing recovery circuit. The RF read signal from the read head is sampled asynchronous to the baud rate and the asynchronous sample values are interpolated to generate sample values that are substantially synchronous to the baud rate. A data detector, such as a Viterbi sequence detector, processes the synchronous sample values to generate an estimated binary sequence representing the recorded binary sequence. The timing recovery circuit comprises a baud rate estimator for estimating the baud rate relative to the sampling rate, wherein the estimated baud rate is used to initialize a timing recovery loop filter at the end of seek operations. The all digital timing recovery circuit and baud rate estimator enable the storage device to begin reading the user data immediately after a seek operation, rather than wait for the CLV servo loop to acquire the target spindle speed.

Abstract: A discrete time servo demodulation technique incorporated within a sampled amplitude read channel to demodulate embedded servo field information stored on a magnetic medium. The servo field information is transduced by a read head into an analog signal, and converted to a sequence of sample values in the read channel. The demodulation technique is responsive to the sample values and includes a discrete time peak detector for detecting servo data, and a discrete time servo burst amplitude detector for measuring the amplitude of servo bursts. Peaks are detected in the analog read signal by sensing a change of slope from the sequence of sample values. The peaks are qualified by polarity in that a peak is detected only if its polarity is opposite in sign from the previous peak. The servo burst amplitudes are measured by interpolating, rectifying, and accumulating the sequence of sample values corresponding to the servo bursts.

Abstract: A quadrature signal generator for optical disk storage devices is disclosed comprising a differential phase detector (DPD) implemented as an adaptive length dual arm correlator. A photo diode generates a light beam for irradiating the optical disk during read operations, and a pair of diagonal signals S1 and S2 are generated by adding a pair of respective quadrants of a four-quadrant photodetector which detects the light beam reflected from the disk. The phase offset between the diagonal signals represents the centerline offset of the light beam from the centerline of a data track recorded on the optical disk. A first and second position error signals (PES) are generated by computing the difference and sum between a positive and negative correlation of the diagonal signals S1 and S2, otherwise referred to as a dual arm correlation (DAC) ##EQU1## where .DELTA. is the correlation offset and L is the correlation length.

Abstract: A system and method for an amplifier control circuit is provided which does not require the use of a large off-chip or on-chip capacitor for achieving a low frequency coupling corner, while still effectively allowing AC coupling the data detection circuit. In addition, the input offset voltage to the amplifier may be compensated and the inherent random low frequency input voltages provided to the amplifier may be controlled or canceled. Further, the amplifier control circuitry includes a freeze capability which allows the control circuitry to halt all updates to the input offset/low frequency control circuit when the voltage input signal is interrupted. In addition low frequency control and offset compensation updates may be performed without causing large output signal glitches so that the integrity of the received signal will not be compromised. In a preferred embodiment the system and method may be utilized for data detection circuits utilized in conjunction with optical disks.

Abstract: A magnetic disk storage device employing an on-the-fly, multiple burst error correction system for detecting and correcting errors in data sectors stored on a magnetic disk, wherein each data sector comprises a data field and multiple sync marks for synchronizing to the data field. Multiple sync marks improve the probability of successful byte synchronization to the data field in the presence of noise in the system, such as defects in the storage medium. Further, a sync mark may be embedded within the data field to facilitate byte resynchronization when synchronization is lost.

Abstract: A partial response class-IV (PR4) sampled amplitude read channel is disclosed for detecting user data and embedded servo data. The detected servo data is encoded using a novel servo code capable of accurately decoding detected codewords representing servo track address during seek operations, even when the recording head flies between two adjacent tracks, and capable of correcting errors in the detected codedwords caused by noise in the read signal, such as inter-symbol interference. In one embodiment, the servo code corrects certain minimum distance error events, such as a bit shift error event, associated with a trellis type sequence detector. To achieve the equivalent effect of a conventional Gray code, the codewords are arranged such that adjacent track addresses differ by a number of bits relative to the minimum distance error events corrected.

Abstract: A system and method is provided to improve the jitter performance of high frequency synthesizers used in read/write channel circuits. The frequency synthesizer is implemented with multiple phase locked loops arranged in a cascaded fashion to increase the update rates at which the cascaded loops operate at for a given frequency resolution of the synthesizer. The cascaded or staged phase locked loops may be utilized for generating read, write, and servo clocks for a read/write channel circuit. The cascaded phase locked loops may also be arranged such that one or more stages are shared to generate the read, write or servo clocks.

Abstract: A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by asynchronously sampling an analog read signal, equalizing the asynchronous sample values according to a desired partial response, and interpolating the equalized sample values to generate synchronous sample values substantially synchronized to a baud rate of the recorded data. The read channel further comprises a gain control circuit which generates a gain error for adjusting the amplitude of the analog read signal to a nominal value through a variable gain amplifier (VGA). During acquisition, the gain error is computed from the asynchronous sample values at the output of the sampling device in order to avoid the delay associated with the discrete equalizer filter and the timing recovery interpolation filter. This decreases the acquisition time and the corresponding length of the acquisition preamble, thereby reserving more area on the disk to record user data.

Abstract: A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated binary sequence from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a read head positioned over the disk storage medium. The read channel comprises a sampling device, such as an analog-to-digital converter (A/D), for sampling the analog read signal to generate the discrete time sample values and for sampling at least one other auxillary analog input signal, such as a servo control signal. In this manner, performance characteristics of the read channel can be measured, such as the driving current applied to the servo control voice coil motor (VCM), without requiring additional hardware.

Abstract: An H configuration write driver circuit is provided which includes integral fault detection circuitry. A load device, such as a magnetic tape recorder write head, is coupled in an H configuration with four drive transistors. A first and second drive transistor are coupled to opposite ends of the load device and produce current flow through the load device in a first direction. A third and fourth drive transistor are coupled to opposite ends of the load device to produce current flow through the load device in the opposite direction. A resistor is coupled in series between each drive transistor and the load device and these resistors serve to determine the time constant of the rise/fall of current through the inductive write head and to limit current flow through a drive transistor in the event of a short circuit condition therein.

Abstract: A cost reduced finite field processor is disclosed for computing the logarithm LOG.sub..alpha. (.alpha..sup.j) of an element of a finite field GF(2.sup.n) using significantly less circuitry than that required by a lookup table typically employed in the prior art. The result of the logarithm (i.e., the exponent of .alpha..sup.j) is represented as a binary number computed serially one bit per clock cycle. In one embodiment, combinatorial logic is used to compute bit 0 of the exponent. On each clock cycle, the exponent is shifted once to the right and bit of the exponent is extracted until the entire exponent has been computed. Shifting the exponent of a field element to the right is carried out by taking the square root of the element. The present invention requires at most n+1 clock cycles to compute LOG.sub..alpha. (.alpha..sup.j), with one embodiment requiring n/2 clock cycles.