Abstract: A system and method for compression of surface normals in three-dimensional graphics data. The method comprises compressing a normal by identifying the location of a first point located at the intersection of the surface of a predetermined sphere (centered on the origin of a set of x-y-z axes) and a vector extended from the origin in a direction specified by the coordinate values of the normal. Identification of the first point includes specifying an index value and one or mapping values. The index value is usable during decompression to identify a second point on the sphere from a plurality of points in a predetermined surface region (such as a predetermined sextant of a predetermined octant region). In one embodiment, the index includes a &thgr; component and a &phgr; component which are usable to locate the second point.

Abstract: A method and graphics system capable of super-sampling and performing real-time convolution to form a soft-edge alpha key are disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to receive 3D graphics data comprising a plurality graphics primitives and then generate a plurality of samples from the 3D graphics data. The samples may comprise both color and alpha information. The super-sampled sample buffer may be coupled to receive and store the samples from the graphics processor. The sample buffer may also be configured to double-buffer at least a portion of each stored sample. The sample-to-pixel calculation unit may be coupled to receive and filter samples from the super-sampled sample buffer to form output pixels and alpha pixels in real time, wherein the alpha pixels are usable to form an alpha key.

Abstract: A graphics system and method for reducing redundant transformation and lighting calculations performed on vertices that are shared by more than one geometric primitive is disclosed. The amount of data transmitted in certain data blocks may be reduced by incorporating a multicast/unicast bit into each data block. This bit may then be set to instruct the control unit to use the current 3D geometry data or state information for subsequent vertices. This may increase efficiency by allowing subsequent vertices using the same 3D geometry data to transfer less data. Conversely, if a vertex has wholly independent 3D geometry data, then its multicast/unicast bit may be set to invoke use of the current 3D geometry data on the current vertex as opposed to all future vertices. The reduction in redundant calculations is accomplished by delaying the formation of geometric primitives until after transformation and lighting has been performed on the vertices.

Abstract: A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.

Abstract: A microprocessor configured to reduce variance in the length of variable length instructions by compressing multiple prefix bytes into a single byte is disclosed. The microprocessor is configured with a predecode unit and an instruction cache. The predecode unit is configured to receive variable length instructions, each having a variable number of prefix bytes. The predecode unit is configured to detect the prefix bytes and compress them into one compressed prefix byte for each instruction. The instruction cache is coupled to the predecode unit and is configured to receive and store the instructions and compressed prefix bytes from the predecode unit. The instruction cache may be configured to output one of the instructions and any corresponding compressed prefix bytes in response to receiving a fetch address. A computer system, method, and software program configured to compress prefix bytes are also disclosed.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.

Abstract: A predecode unit is configured to predecode a fixed number of instruction bytes of variable length instructions per clock cycle. The predecode unit outputs predecode bits which identify the start byte of an instruction. An instruction alignment unit uses the start bits to dispatch the instructions to a plurality of decode units that form fixed issue positions. In one embodiment, the predecode unit identifies a plurality of length vectors. Each length vector is associated with one of the instruction bytes predecoded in a clock cycle and identifies the length of an instruction if an instruction starts at the instruction byte corresponding to the length vector. A tree circuit determines in which instruction bytes instructions start.

Abstract: A microprocessor configured to rapidly decode variable-length instructions is disclosed. The microprocessor is configured with a predecoder and an instruction cache. The predecoder is configured to expand variable-length instructions to create fixed-length instructions by padding instruction fields within each variable-length instruction with constants until each field reaches a predetermined maximum width. The fixed-width instructions are then stored within the instruction cache and output for execution when a corresponding requested address is received. The instruction cache may store both variable- and fixed-width instructions, or just fixed-width instructions. An array of pointers may be used to access particular fixed-length instructions. The fixed-length instructions may be configured to all have the same fields and the same lengths, or they may be divided into groups, wherein instructions within each group have the same fields and the same lengths.

Abstract: A microprocessor capable of predecoding variable-length instructions and storing them in a three-dimensional instruction cache is disclosed. The microprocessor may comprise a predecode unit, an instruction cache, and an address translation table. The predecode unit receives variable-length instructions from a main memory subsystem. These instructions are then predecoded by detecting instruction field boundaries within each variable-length instruction. Instructions fields that are not present in a particular instruction may be added by inserting padding constants so that the instruction matches a predetermined format having all instruction fields. The predecoded instruction is stored in the instruction cache, which may be logically and physically structured as a three-dimensional array. Each instruction is stored in the cache so that it has a fixed length in two dimensions. The address translation table maintains address translations for each instruction stored in the instruction cache.

Abstract: A method for storing mip map series in a multi-bank texture memory is disclosed. Each mip map has a different size and represents a different resolution version of a texture map image that is to be mapped onto a three dimensional object comprising one or more polygons. To prevent page faults when accessing corresponding texels in consecutive mip maps, each mip map is divided in two halves. The halves are stored in different banks of the multi-bank texture memory. The banks used are alternated so that corresponding texels in consecutive mip maps are stored in different memory banks. Mip maps may be categorized as large or small, with all small mip maps after the first being stored in their entirety in one memory bank. Small mip maps are those that are equal to or smaller than the page size of the multi-bank texture memory. A computer system, graphics subsystem, and software program capable to efficiently store mip map series in a multi-bank texture memories are also disclosed.

Abstract: A microprocessor having an instruction queue capable of out-of-order instruction dispatch and rapidly selecting one or more oldest eligible entries is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations and may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. The microprocessor may be further configured with high speed control logic coupled to the instruction queue. The control logic may comprise a number of pluralities of multiplexers, wherein the first plurality of multiplexers are configured to select a first subset of the instructions stored in the queue. The second plurality of multiplexers then select a second subset of instructions from the first subset.

Abstract: A microprocessor configured to predecode instructions with variable address and operand lengths into a uniform format with constant address and operand lengths is disclosed. The microprocessor may comprise a predecode unit configured to receive instruction bytes from a main memory subsystem. The predecode unit is configured to detect instructions having prefix bytes that override default operand and address field lengths. This information, combined with the instruction's default operand and address length, allows the predecode unit to expand addresses and operands that are shorter than the predetermined uniform length. The operands and addresses are expanded by padding them with constants. Once the instructions are padded to a uniform format, they are stored in an instruction cache. An address translation table may be used to translate fetch addresses, thereby compensating for the offset created by the padding constants.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

Abstract: A microprocessor capable of out-of-order instruction decoding and in-order dependency checking is disclosed. The microprocessor may include an instruction cache, two decode units, a reorder queue, and dependency checking logic. The instruction cache is configured to output cache line portions to the decode units. The decode units operate independently and in parallel. One of the decode units may be a split decoder that receives all instruction bytes from instructions that extend across cache line portion boundaries. The split decode unit may be configured to reassemble the instruction bytes into instructions. These instructions are then decoded by the split decode unit. A reorder queue may be used to store the decoded instructions according to their relative cache line positions. The decoded instructions are read out of the reorder queue in program order, thereby enabling the dependency checking logic to perform dependency checking in program order.

Abstract: A cache memory configured to access stored instructions according to basic blocks is disclosed. Basic blocks are natural divisions in instruction streams resulting from branch instructions. The start of a basic block is a target of a branch, and the end is another branch instruction. A microprocessor configured to use a basic block oriented cache may comprise a basic block cache and a basic block sequence buffer. The basic block cache may have a plurality of storage locations configured to store basic blocks. The basic block sequence buffer also has a plurality of storage locations, each configured to store a block sequence entry. The block sequence entry may comprise an address tag and one or more basic block pointers. The address tag corresponds to the fetch address of a particular basic block, and the pointers point to basic blocks that follow the particular basic block in a predicted order.

Abstract: A microprocessor having an instruction queue capable of out-of-order instruction dispatch and compaction of unaligned strings of empty storage locations is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations, each coupled to a single destination storage location. The instruction queue may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. As the instructions are output, gaps of empty storage locations may be formed in the queue. The microprocessor may be configured to compact out strings of empty storage locations greater than a predetermined number. This compaction may be performed by selectively shifting the instructions remaining in the queue either zero or N storage locations, wherein N is a predetermined positive integer.

Abstract: A multiplier capable of performing complex iterative calculations such as division and square root concurrently with simple independent multiplication operations is disclosed. The division and square root operations are performed using iterative multiplication operations such as the Newton Raphson iteration and series expansion. These iterative calculations may require a number of passes through the multiplier. Since the multiplier may be pipelined, it may experience a number of idle cycles during the iterative calculations. The multiplier is configured to utilize these idle cycles to perform independent simple multiplication operations. The multiplier may be configured to assert a control signal that is indicative of future idle cycles in the first stages of the multiplier pipeline. The control signal may be used by control logic to dispatch independent simple multiplication operations to the multiplier for execution during the idle clock cycles.

Abstract: A microprocessor configured to use historical scan information to speed instruction scanning is disclosed. The microprocessor may comprise an instruction cache, a scanning history table, routing logic, and two or more scanning units. The instruction cache is configured to output sequences of stored instruction bytes in response to receiving corresponding fetch addresses. The scanning history table, which may also receive the fetch addresses, is configured to output corresponding stored scan block boundary information. The routing logic, which is coupled between the instruction cache, scanning history table, and scanning units, is configured to route the first N instructions to the first scanning unit, and the second N instructions to the second scanning unit, wherein N is a predetermined integer greater than one. The scanning units are configured to operate independently and in parallel.