Abstract: Method and system for implementing an inter-domain constraint-based shortest path first (“IrD-CSPF”) technique for supporting hierarchical routing in interconnected multi-domain OTNs are described. In one embodiment, the invention is a method for calculating a network path in an interconnected multi-domain network. The method comprises receiving a path setup request message for a new traffic flow in the network identifying a source node in one domain of the network and a destination node in a second domain of the network; determining a common ancestor hierarchical routing domain that includes ancestor nodes of both the source and destination nodes; calculating an inter-domain path from one ancestor node to the other ancestor node that determines, for each lower-level domain, border nodes in the domain from the source node to the destination node; and for each bottom-level domain, calculating an intra-domain path between the border nodes that were determined for the domain.

Abstract: System and method for compensating for DS0 timing source transients, such as may occur during a switchover to a new external reference, is described. In one embodiment, an SFI control signal is monitored for embedded frame position information. When the frame position information is initially detected, a 10-bit frame clock counter is reset to zero. The counter is then incremented using an 8.192 MHz clock. From that point on, each time the SFI frame position information is detected, the value of the frame clock counter is checked. If the counter value is zero, the counter continues to run freely. If the counter value is non-zero and the most significant bit (“MSB”) thereof is zero, the count of the frame clock counter is held for one clock period. If the counter value is non-zero and the MSB thereof is one, the count of the frame clock counter is advanced by a value of two, rather than one, for one clock period.

Abstract: A technique for embedding a first clock phase within a second signal is described. In one embodiment, the invention comprises a method of embedding a phase of a first signal within a second signal comprising the steps of monitoring a first signal for a frame event, responsive to detection of a frame event in the first clock signal, determining a position of the frame event relative to a current segment of a second signal, and embedding in the current segment of the second signal a value representative of the relative position of the detected frame event.

Abstract: A scheduling system and methodology for use in a network switch element having multiserver, multiple-arbiter architecture. Ingress ports and egress ports coupled to the cross-connect fabric of the network element are provided with multiple ingress and egress arbiters, respectively, for effectuating an iterative arbitration strategy such as RGA or RG. Arbiter architectures include singe-arbiter-per-port; single-arbiter-per-server; multiple-arbiters-per-port; and multiple-arbiters-per-server arrangements, wherein the arbiters can be implemented using RRA, BTA, Flexible Ring, or any other arbiter technology. Depending on the iteration strategy, ingress arbiter architecture and egress arbiter architecture, a variety of iterative, multiserver-capable scheduling algorithms can be obtained, which scheduling algorithms can also be implemented in QoS-aware network nodes.

Abstract: A system and method for transporting IN/AIN signaling (e.g., SS7 signaling) over an IP-based network using Stream Control Transmission Protocol (SCTP), wherein a peer-to-peer protocol adaptation (PPA) structure is provided at a signaling node. The PPA structure includes an interworking functionality between an MTP3 layer and the SCTP messaging, and operates to provide a symmetrical MTP2 adaptation interface therebetween. The PPA interface functionality facilitates the implementation of network management capabilities included in the MTP3 layer such that the advantageous features of SS7 signaling are retained in the SCTP transport. The MTP2 adaptation interface functionality is processed locally with respect to the signaling node, rather than backhauling the associated signaling to an external node via an IP connection.

Abstract: A wavelength agile optical transponder system and method for testing a fiber optic link formed of a single fiber. An optical source coupled to the optic link provides a signal at a first wavelength which is propagated towards a wavelength division multiplex (WDM) coupler disposed on the optic link. Upon receiving the optical signal by a receiver, an optical cross-connect arrangement is utilized for transmitting the optical signal after translating its wavelength into a second wavelength. By evaluating the optical signal in the optical loop-back thus effectuated, the path integrity of the optic link is determined without having to know the wavelength of the incident signal or direction of transmission.

Abstract: A bus control module as a terminal stage for a multi-stage clock/alarm distribution scheme in a signaling server organized into addressable shelves. A system timing generator provides a framed serial control signal, SFI, addressing hierarchically arranged clock distribution modules and the bus control modules, to distribute a system clock to the bus control modules. Each bus control module provides a copy of the system clock to line cards with which it interfaces. The bus control module reports alarms and status signals from its line interface cards to the system timing generator using another framed serial signal. The bus control module forwards upstream towards the system timing generator a clock signal selected from clocks signals recovered by its line interface cards from received network signals.

Abstract: A multi-stage clock distribution scheme for use in a signaling server organized into a plurality of uniquely addressable shelves. The signaling server includes a system timing generator, one or more clock distribution modules arranged in a nested hierarchical manner, and a plurality of bus control modules, wherein each bus control module interfaces with at least a portion of line cards disposed in a shelf. The system timing generator provides a framed serial control signal, SFI, for controlling the operation of the multi-stage clock distribution scheme. The SFI signal encodes the IDs of the clock distribution modules and bus control modules whereby a system clock generated by the system timing generator based on a select reference input is successively fanned-out by the intermediate clock distribution modules based on address and ID information encoded in select fields of the SFI frames until the fanned-out system clocks are received by the bus control modules.