Abstract: An integrated circuit identification device (ICID) to be incorporated into an integrated circuit (IC) includes an array of electronic cells in which the magnitude of an output signal of each cell is a function of randomly occurring parametric variations which vary from cell-to-cell. The ICID also includes a circuit for measuring the output of each cell and for producing output data having a value reflecting the particular combination of measured characteristics of all of the elements of the array. When we make the number of elements in the array large enough, we insure that to a high degree of probability, the pattern of measured array cell characteristics for an ICID embedded in any one IC will be unique and distinguishable from such patterns measured by ICIDs embedded in millions of other ICs. Thus the value of the output data produced by an ICID circuit acts as a unique "fingerprint" for the IC in which it is installed, and can be used as a unique identification (ID) for that IC.

Abstract: A system for stabilizing a delay through a signal path of an integrated circuit (IC) includes an oscillator for producing a periodic first reference signal, a delay circuit for delaying the first reference signal to produce a periodic second reference signal, and a loop controller for adjusting the magnitude of the IC's power supply so as to maintain a constant phase difference between the first and second reference signals. By adjusting the power supply magnitude, the loop controller also stabilizes signal path delays through logic circuits implemented in the IC. The oscillator is formed by a logic gate implemented in the IC and a passive delay line feeding the logic gate's output back to its input. The delay of the delay circuit is programmably adjustable to allow for adjustment of the signal path delay through the IC.

Abstract: A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR) supplied as input thereto. An instruction processor receives each instruction read out of the instruction memory and alters the address input to the instruction memory in accordance with the received instruction so that the instruction memory reads out a next instruction. The instruction processor, which includes a conventional return address stack, is capable of executing conventional address increment, call and return instructions. The instruction processor is also capable of executing a temporary return instruction (TEMP) by incrementing its current address output to produce a new return address, by setting its address output to the value of a return address previously saved in the stack, by popping the saved return address from the stack, and by pushing the new return address onto the stack.

Abstract: An integrated circuit (IC) tester includes a set of digital and analog channels, each of which may be programmed to carry out a sequence of test activities at pins of an IC under test. The channels are interconnected by a trigger bus, and each channel may be programmed to respond to a detected event during a test by transmitting a particular trigger code to every other channel via the trigger bus. Each channel may be also programmed to respond to a particular trigger code arriving on the trigger bus by branching its sequence of test activities. Thus any channel detecting an event during a test can signal all other channels to immediately terminate a current sequence of test activities and branch to another set of test activities. Such a conditional branch capability enables the tester to automatically perform an "if/then" diagnostic test on an IC in which a test result detected at any point during the test determines the future course of the test.

Abstract: A cooling system for an electronic equipment enclosure employs a flat plate heat pipe to deliver heat from the interior of the enclosure through a connector to a removable external heat sink. The heat pipe includes a metallic bottom plate having a depression therein containing a set of rods evenly spaced from one another. A top plate covers the bottom plate with the rods compressed therebetween. Channels formed between adjacent rods are partially evacuated and injected with an evaporative fluid. The fluid and its vapor circulate in the channels to convey heat from a warm end of the heat pipe to a cool end. The heat sink is of similar construction.

Abstract: A dynamically configurable network buffer includes a buffer manager organizing a buffer memory into a set of uniform sized packet buffers, each of which is large enough to store the largest possible data packet that may be transmitted through the network switch. The buffer manager further subdivides each packet buffer into a set of smaller packet cells of uniform size. When an incoming data packet arrives at the network buffer, the buffer manager determines its size. If the packet is too large to be stored in a single packet cell, the buffer manager stores the packet by itself in an unoccupied packet buffer. If the packet is small enough to be stored in a single packet cell, the buffer manager stores the packet in an unoccupied packet cell. The network buffer can increase or decrease packet cell size in response to input configuration data.

Abstract: A programmable and precise voltage-to-current converter (a.k.a. current source) that tracks temperature variations is presented. The voltage-to-current converter is implemented by placing a voltage reference circuit between the bases of the two transistors, or alternatively between a diode and a transistor, in a voltage controlled current source circuit which can be adjusted to track temperature variations. In one embodiment, the voltage reference circuit is a programmable digital-to-analog (D/A) converter. In a second embodiment, the voltage reference circuit is a differential amplifier.

Abstract: A self-balancing temperature control device for an integrated circuit (IC) includes a heat sink attached to the IC having thermomorphic fins or vanes. When the IC increases its heat output, the fins or vanes warm up and change their shape in a manner that increases the rate at which heat is removed from the IC.

Abstract: Noise factor of a radio-frequency device under test (DUT) is determined by driving the input of the DUT with a randomly modulated sine wave and measuring the power of a resulting DUT OUTPUT signal within each of a set of equally-sized frequency bands. The noise factor is computed as a combination of the power of the modulated sine wave within each of a plurality of frequency bands and the measured power of the DUT OUTPUT signal within that same plurality of frequency bands.

Abstract: Plant resin exuded by poison ivy, poison oak, poison sumac and other plant resins are removed from the skin by successive applications of an alkaline cleanser and acidic stripper. The skin is first thoroughly washed with the alkaline cleanser. After rinsing the cleanser from the skin, the skin is daubed with the acidic stripper. The alkaline cleanser is a mixture of water, soap, turpentine, a mild abrasive, and mineral spirits. The acidic stripper is a mixture of an acid, and astringents such as tannin and witch hazel extract.

Abstract: A programmable phase shifter includes a tapped delay line for successively delaying a periodic reference signal to produce a set of phase distributed tap signals. A multiplexer selects one of the tap signals as input to a programmable delay circuit which further delays the selected tap signal to produce an output signal that is phase shifted from the reference signal. A programmable data converter converts input data indicting a desired phase shift between the reference signal and the output signal into data for controlling the multiplexer selection and the amount of delay provided by the programmable delay circuit. The relationship between conversion table input and output data is adjusted so that the period of the output signal has a desired linear relationship to the input data value.

Abstract: An asynchronous integrated circuit (IC) tester includes a set of channels interconnected by a runtime bus. Each channel accesses a separate terminal of an IC device under test (DUT) for carrying out test activities during successive cycles of a test. During each cycle of a test, each channel may transmit a test signal to the DUT, sample a DUT output signal and store sample data representing the logic state of the DUT output signal, and/or compare previously stored sample data to expected patterns to determine if the DUT is operating correctly. Any channel may be programmed to place a MATCH code on the runtime bus when it recognizes, or fails to recognize, a particular logic pattern in the DUT output signal. Other channels may be programmed to pause their comparison activities until they receive the MATCH code over the runtime bus. Thus a DUT output signal event detected by any one channel triggers test activities by other channels.

Abstract: An integrated circuit (IC) tester organizes an IC test into a succession of test cycles, each test cycle being subdivided into four segments. The tester includes a separate tester channel for carrying out a test activity at each IC pin during each segment of the test cycle. The tester also includes a separate pattern generator for each channel. Each pattern generator concurrently generates four vectors at the start of each test cycle. Each vector tells the channel what activity it is to carry out during a separate segment of the test cycle. Each pattern generator includes a low-speed vector memory storing large blocks of vectors at each address and a cache memory system for caching blocks of vectors read out of the vector memory at a low frequency and then reading vectors out in sets of 16 at the higher test cycle frequency. A vector alignment circuit selects from among the cache memory output vectors to provide the four vectors to the channel for the test cycle.

Abstract: A triggered clock signal generator produces a periodic output clock signal (CLOCK3) in response to an input TRIGGER signal, wherein a delay between the TRIGGER signal and the first pulse of the CLOCK3 signal is accurately adjustable. The apparatus includes a period generator and a phase adjuster. The period generator, using a periodic input signal (CLOCK1) as a timing reference, responds to the TRIGGER signal by producing a periodic output clock signal (CLOCK2) in adjustably delayed response to a next pulse of the CLOCK1 signal. The phase adjuster phase shifts the CLOCK2 signal to produce the CLOCK3 signal. The phase adjuster compares the phase of the CLOCK1 signal to the phase of the TRIGGER signal to determine an appropriate amount by which to phase shift the CLOCK2 signal so that the time delay between the TRIGGER signal and the first pulse of the CLOCK3 signal is independent of the phase relation between the TRIGGER and CLOCK1 signals.

Abstract: A method of operating an integrated circuit (IC) tester is disclosed in which an IC is repeatedly tested with respect to a limited number of combinations of values of two variable IC operating parameters (X and Y) to determine the boundary of a two-dimensional range of combinations of values of the X and Y parameters for which the IC passes a test. After finding a combination of X and Y parameter values on the boundary, each combination of parameter values to be tested thereafter is selected by altering either the X or Y parameter value, with the decision based on whether the IC passed the last test and on the manner in which a last tested combination of X and Y parameter values was selected.

Abstract: A test head for an integrated circuit tester includes a set of wedge-shaped node cards, one for each terminal of the integrated circuit device under test (DUT). Each node card holds circuits for carrying out all test activities at one DUT terminal including generating and transmitting a test signal to the DUT and receiving and processing a response signal produced by the DUT. The test and response signals pass through an I/O terminal at a narrow end of the node card. A card frame having hemispherical inner and outer shells holds the node cards substantially therebetween with the I/O terminal of each card protruding through an aperture in the inner shell. A centroid distributor having substantially a hemispherical shaped surface nesting within the inner shell of the card frame holds a set of first terminals in contact with the node card I/O terminals. A set of conductors within the centroid distributor interconnect each first terminal with a corresponding second terminal on a flat surface of the distributor.