Abstract: An emergency location marker system for capsized vessels is housed in an emergency location marker canister or container (10) secured by a bracket (22) to an exposed or outside surface of the vessel (60). An inflatable aerial location marker (40) is deflated and folded in the small space of the canister. The aerial location marker is formed to provide upon inflation a relatively large surface area flat configuration to blanket a sufficient area of the sea surface for high visibility. The high visibility sea surface area blanketing marker (40) is formed with at least one flexible joint (41) for responding flexibly to wave motion while adhering to the sea surface. The sea surface area marker may be in a flat circular configuration, for example six feet in diameter and formed with a high visibility color. Flexible joints (41) along intersecting diameters permit flexing of the flat circular configuration marker in response to waves from all directions.

Abstract: An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor element with the current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element. A first output voltage sensing switching circuit is coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements. The secondary pulldown transistor element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer first. A relatively small discharge current is therefore initiated from the output before turn on of the relatively large discharge current of the primary pulldown transistor element.

Abstract: A translator-translator logic (TTL) to emitter coupled logic or current mode logic (ECL/CML) input buffer and translator circuit provides temperature compensated input and threshold signal voltage levels to a translator circuit ECL gate for improved operation of the translator circuit. A threshold clamp circuit is coupled between an on-chip band-gap bias generator and the base node of the reference transistor element of the translator circuit ECL gate. The threshold clamp circuit maintains a substantially fixed temperature compensated reference voltage or threshold voltage level at the base node of the reference transistor element, referenced to the temperature compensated current source voltage level V.sub.cs from the bias generator. An input clamp circuit also references the logic high signal voltage level V.sub.TH at the base node of the ECL gate input transistor element to V.sub.CS.