Patents Represented by Attorney, Agent or Law Firm Daniel N. Fishman
  • Patent number: 6501848
    Abstract: A method for in-room computer reconstruction of a three-dimensional (3-D) coronary vascular tree from routine biplane angiograms acquired at arbitrary angles and without using calibration objects.
    Type: Grant
    Filed: November 20, 1999
    Date of Patent: December 31, 2002
    Assignee: University Technology Corporation
    Inventors: John Carroll, Shiuh-Yung James Chen
  • Patent number: 6445717
    Abstract: Data which is transmitted over the internet or other transmission networks is first divided up into individual information packets, transmitted and then reassembled into useful data after reception. Parity packets are included in with the information packets in the transmission of data in order to enable the regeneration of any information packets which were lost or damaged during transmission. The grouping of information packets and parity packets derived therefrom is termed a chunk. Chunk arrangements to recover from all cases of single and double lost packets are disclosed. Bursts of lost packets are recovered by interleaving the transmission of packets from different chunks. If the recovery is not successful then retransmission occurs in a manner similar to TCP.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: September 3, 2002
    Assignee: Niwot Networks, Inc.
    Inventors: William A. Gibson, George E. Noble, Chris J. Stearns
  • Patent number: 6424111
    Abstract: A robotic library design for a mechanism that picks and places storage cartridges having a robotic shuttle assembly that moves parallel to the storage cartridges, a moveable stage that moves perpendicular to the storage cartridges, and a pair of gripping finger to retain, extract, and deposit the storage cartridges within the library subsystem. The pair of gripping fingers, initially biased in a closed position, are cammed open by the edges of the storage cartridge upon the moveable stage's approach and close upon engagement with the storage cartridge's notched recesses. The storage cartridge is moved within the library subsystem and is delivered to its destination when a solenoid activates a mechanical trigger that releases the pair of gripping fingers. The moveable stage completes the storage cartridge's delivery and resets for its next instruction.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: July 23, 2002
    Assignee: Breece Hill Technologies, Inc.
    Inventor: Alan D. Romig
  • Patent number: 6356864
    Abstract: The present invention is a methodology for analyzing and evaluating a sample text, such as essay(s), or document(s). This methodology compares sample text to a reference essay(s), document(s), or text segment(s) within a reference essay or document. The methodology analyzes the amount of subject-matter information in the sample text, analyzes the relevance of subject matter information in the sample and evaluates the semantic coherence of the sample. This methodology presumes there is an underlying, latent semantic structure in the usage of words. The method parses and stores text objects and text segments from the sample text and reference text into a two-dimensional data matrix. A weight is computed for each text object and applied to each data matrix cell value. The method performs a singular value decomposition on the data matrix, which produces three trained matrices. The method computes a vector representation of the sample text and reference text using the three trained matrices.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: March 12, 2002
    Assignee: University Technology Corporation
    Inventors: Peter William Foltz, Thomas K. Landauer, Robert Darrell Laham, II, Walter Kintsch, Robert Ernest Rehder
  • Patent number: 6324586
    Abstract: A synchronized timing system is disclosed for one or more of a plurality of network interconnected computers. The system utilizes a global satellite system and includes a receiver device for detecting out-of-phase signals from a plurality of satellite sources of the satellite system. A mechanism is provided for processing and phase correlating these signals to generate a single absolute time reference signal therefrom. An interface device is disposed in each computer for receiving the reference signal and adapting this signal as the internal master clock reference for the operating system of the computer. Finally, a mechanism interconnects each computer in the network of computers to synchronize the internal master clocks of the computers to the absolute time reference signal to create a plurality of network interconnected time synchronized computers.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: November 27, 2001
    Inventor: Aric R. Johnson
  • Patent number: 6132922
    Abstract: A high viscosity, high solid volume liquid ink for use in electrophotographic printing systems. A silicone oil carrier material is combined with toner particles (including pigment, binder polymers and charge control agents) in a ratio of about 45% toner particles to 55% carrier liquid. The resultant ink preferably has a viscosity in the range 30000 to 50000 cs. The high viscosity ink of the present invention is preferably applied to a photoconductor material having a latent charged image thereon and a thin pre-wet material applied thereto. The pre-wet material is preferably a low viscosity silicone oil material. The composite layer of the combined low viscosity pre-wet and high viscosity ink permits the polymerized toner particles to migrate toward the latent charged image on the photoconductor surface. The high viscosity ink of the present invention helps maintain uniform dispersion of the toner particles in the liquid carrier.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: October 17, 2000
    Assignee: Advanced Color Technology, Inc.
    Inventors: Kensuke Fukae, Ichiro Yoshida
  • Patent number: 5983306
    Abstract: A bus bridge circuit having at least one register to store address ranges to enable or disable prefetch in upstream memory read transactions or upstream write transaction buffering/posting data to specific devices. The use of address ranges allows the present invention to provide selectable control of prefetch for upstream memory read transaction flow. This feature allows the continued use of read prefetch for targets that allow upstream read prefetch while disabling upstream read prefetch for targets that do not allow upstream read prefetch. Additionally, the use of the address range allows upstream memory write transaction flow without utilizing data buffering or posting for specific targets. This feature provides immediate delivery of upstream data to selected targets by selectively disabling buffering/posting of upstream memory write commands as performed by a FIFO buffer.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: November 9, 1999
    Assignee: LSI Logic Corporation
    Inventors: Brian E. Corrigan, Alan D. Rymph
  • Patent number: 5944838
    Abstract: A redundant storage control module (also referred to as RDAC or multi-active controller) maintains a queue of pending I/O requests sent for processing via a first asynchronously operating I/O path. In the event of failure of the first asynchronously operating I/O path, the controller restarts the entire queue of pending I/O requests to a second I/O path without waiting for each request to individually fail from the first path. Some prior techniques required the RDAC module to await failure of each I/O request sent to the failed first I/O path before restarting each failed request on the secondary I/O path. Such techniques greatly extend the total time required to restart all operations sent to a failed I/O path, by awaiting the failure of all I/O requests previously sent to the first I/O path.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: August 31, 1999
    Assignee: LSI Logic Corporation
    Inventor: Ray M. Jantz
  • Patent number: 5937174
    Abstract: A cache memory control architecture within a RAID storage subsystem which simplifies the migration and porting of existing ("legacy") control methods and structures to newer high performance cache memory designs. A centralized high speed cache memory is controlled by a main memory controller circuit. One or more bus bridge circuits adapt the signals from the bus architecture used by the legacy systems to the high speed cache memory. The bus bridge circuits each adapt, for example, a PCI bus used for a particular cache access purpose to the signal standards of an intermediate shared memory bus. The main memory controller circuit adapts the signals applied to the intermediate shared memory bus to the high speed cache memory bus. The hierarchical bus architecture permits older "legacy" control methods and structures to be easily adapted to newer cache memory architectures.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: August 10, 1999
    Assignee: LSI Logic Corporation
    Inventor: Bret S. Weber
  • Patent number: 5933824
    Abstract: Methods and associated apparatus for coordinating file lock requests from a cluster of attached host computer systems within I/O controllers (e.g., intelligent I/O adapters) attached to a storage subsystem. The I/O controllers, operable in accordance with the methods of the present invention, includes semaphore tables used to provide temporary exclusive access to an identified portion of an identified file. The host systems request the temporary exclusive access of a file through the I/O controllers rather than over slower network communication media and protocols as is known in the art. The I/O controllers then manages a plurality of competing lock requests to provide mutual exclusivity of the file access. The file lock management is therefore managed over the higher bandwidth storage interface channels of the host systems and without the generalized network protocols burdening the lock management process and the host system CPUs.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: August 3, 1999
    Assignee: LSI Logic Corporation
    Inventors: Rodney A. DeKoning, Gerald J. Fredin
  • Patent number: 5917723
    Abstract: A method for transferring data from a first device to a second device where the second device has a main data processor and a secondary processor associated therewith. The method includes the steps of (1) transferring a data stream having a control portion and a data portion from the first device to the second device, and (2) processing the data portion with the secondary processor in accordance with the control portion without interrupting the main data processor. A multi-controller apparatus which is useful for practicing the method is also disclosed.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: June 29, 1999
    Assignee: LSI Logic Corporation
    Inventor: Charles D. Binford
  • Patent number: 5895493
    Abstract: Methods and associated apparatus for maintaining management information pertaining to a storage subsystem attached to a plurality of host systems. In particular, the present invention stores configuration and other management information regarding a storage subsystem in a reserved area of the storage subsystem called a host store region (HSR). The configuration information is timestamped by the storage subsystem when stored in the HSR. The information written therein is written and read by attached host systems using standard read and write commands directed specifically to the HSR. The storage subsystem has a reserved area distinct from the storage capacity used for persistent storage of host supplied data. A portion (the HSR) of this reserved area is set aside as a scratchpad for use by all attached host systems to communicate management information among one another. The present invention uses the existing communication channel between each of the attached host systems and the common storage subsystem.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: April 20, 1999
    Assignee: LSI Logic Corporation
    Inventor: Juan C. Gatica
  • Patent number: 5881254
    Abstract: A bus bridge circuit having a memory port integrated therewith for upstream memory access independent of the activity on the primary bus connected to the bridge circuit. In a preferred embodiment, the present invention adds a memory port to a PCI bridge circuit usable for upstream data transfers to an attached cache memory subsystem. The memory port of the present invention is preferably 64 bits wide to permit high speed data access to the shared cache memory subsystem. An alternative embodiment of the present invention implements a 128 bit wide data path to an attached high speed cached memory subsystem. The memory port of the present invention utilizes FIFO devices to isolate the memory port transactions from the secondary bus transactions. This FIFO design of the memory port allows bursting of high speed transfers to the shared memory, independent of activity on the primary bus, while minimizing the performance impact on the secondary bus.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: March 9, 1999
    Assignee: LSI Logic Corporation
    Inventors: Brian E. Corrigan, Alan D. Rymph
  • Patent number: 5875343
    Abstract: Apparatus and associated methods for improving I/O performance in a computing system which includes one or more MPUs and one or more IOPs. I/O requests are queued by a requesting MPU in a memory shared with one or more IOPs. Each IOP is associated with a queue. Each IOP may continue processing queued I/O requests after completing processing on an earlier request. In addition, each MPU is associated with a queue shared with the IOPs. When an IOP completes processing of an I/O request, a completion message is added to the requesting MPU's queue and an interrupt is generated for that MPU. The MPU services all completion messages in its queue when the interrupt is processed. A threshold value is associated with each MPU queue. The threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the MPU.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: February 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Charles D. Binford, Michael J. Gallagher, Craig C. McCombs
  • Patent number: 5867736
    Abstract: Methods operable in a SCSI RAID subsystem to enable improved portability in host based RAID management programs. RAID management programs which provide an administrative user interface for managing the operation and configuration of a RAID subsystem have traditionally communicated with the RAID system using control function calls (ioctl) through the operating system's device driver. Ioctl function calls are notoriously non-standardized among different operating systems and even among different versions of certain operating systems. The methods of the present invention are operable within a RAID subsystem to enable use of standardized read and write system function calls to the device driver for communication with a control port within the RAID subsystem. A special LUN is reserved for such read and write administrative calls. The special control port LUN processes the read and write calls to perform the desired RAID management functions on behalf of the management program on an attached host computer.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: February 2, 1999
    Assignee: LSI Logic Corporation
    Inventor: Ray M. Jantz
  • Patent number: 5860091
    Abstract: Methods and associated apparatus in a RAID storage subsystem to enhance the performance of write operations for sequences of large buffers generally non-aligned with stripe boundaries in the RAID storage subsystem. In particular, the methods identify a starting non-aligned portion of each large buffer to be written to the RAID storage subsystem, an ending non-aligned portion of each large buffer to be written to the RAID subsystem, and a larger middle portion of the large buffer to be written to the RAID subsystem which is aligned with stripe boundaries of the RAID storage subsystem. The stripe-aligned middle portion is written to the RAID storage devices in a cache write through mode using stripe write operations to maximize data throughput. The starting and ending portions identified by the methods of the present invention are written to the cache memory in a write back mode such that they will eventually be posted to the RAID storage devices in due course through normal RAID processing.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: January 12, 1999
    Assignee: Symbios, Inc.
    Inventors: Rodney A. DeKoning, Gerald J. Fredin
  • Patent number: 5822782
    Abstract: Methods and associated apparatus operable in a RAID subsystem to improve the speed and flexibility of initializing the subsystem by storing configuration and identification information in a reserved area on each disk drive in the subsystem. The reserved area on each disk drive of the disk array contains a unique identifier to identify the particular disk drive from all others and further contains group configuration information regarding all groups in which the particular disk drive is a member. The configuration and identification information is generated and written to each disk drive in the disk array when the particular disk drive is configured so as to be added or deleted from groups of the subsystem. Upon subsystem reset (e.g. power on reset or other reset operations), the RAID controller in the subsystem determines the proper configuration of the RAID groups despite temporary unavailability or physical relocation of one or more disk drives in the disk array.
    Type: Grant
    Filed: October 27, 1995
    Date of Patent: October 13, 1998
    Assignee: Symbios, Inc.
    Inventors: Donald R. Humlicek, John R. Kloeppner, Grover G. Phillips, Curtis W. Rink
  • Patent number: 5790773
    Abstract: Methods and apparatus for the rapid generation of a snapshot copy of the data stored in a RAID storage subsystem. In addition to the users configured RAID logical units, the present invention provides for the definition within the RAID controller of a logical RAID level one device having an operational half comprising the users defined logical unit(s) and having a non-operational mirror component. The user access data stored on the RAID subsystem by direct access to the users defined logical units. When a user directs a snapshot copy request to the operational, user defined logical units, the RAID controller responds by temporarily configuring available storage capacity (e.g. spare disk drives) in the RAID subsystem to perform the function of the non-operational mirror component of the logical RAID level one device.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: August 4, 1998
    Assignee: Symbios, Inc.
    Inventors: Rodney A. DeKoning, Donald R. Humlicek
  • Patent number: 5787242
    Abstract: Methods and apparatus for moving pinned data corresponding to a temporarily dead RAID device between the cache memory of a RAID subsystem and a log area. In response to detection of a dead RAID device within a RAID subsystem, the methods of the present invention move any pinned data from the cache memory of the RAID controller to a log area preferably allocated on the disk space of one or more operational RAID devices within the subsystem. In response to revival of the dead RAID device methods of the present invention restore the logged, pinned data from the log area of the operational RAID device(s) to the cache memory as dirty data ready for posting to the revived RAID device. The log area may be either permanently allocated within the RAID subsystem, or may be dynamically allocated in response to recognition of the dead RAID device and freed in response to revival of the RAID device.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: July 28, 1998
    Assignee: Symbios Logic Inc.
    Inventors: Rodney A. DeKoning, Donald R. Humlicek, Max L. Johnson
  • Patent number: 5781769
    Abstract: A method and associated apparatus for using a content addressable memory (CAM) to process timed events in a process control application. A time value field in each CAM entry identifies the time at which a corresponding event is to be processed. An event identifier field in each CAM entry identifies the event to be processed. A time value generator applies signals indicative of a time value to the CAM. The CAM returns as data on its output signal paths any entries whose time value fields correspond to the applied time value signals. The event identifier field applied to the output signal paths of the CAM is then applied to the process controller to identify an event to be processed. The methods and apparatus of the present invention are applicable, for example, in communication controller devices wherein a protocol requires timed event processing for standardized communications (e.g., Fibre Channel or FDDI).
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: July 14, 1998
    Assignee: Symbios, Inc.
    Inventor: David M. Weber