Abstract: A novel bias voltage generating circuit and method are disclosed. In one embodiment, the bias voltage generating circuit includes a first transistor with a base terminal coupled to the output node and an emitter terminal coupled to ground. The circuit also includes a resistor with a first terminal coupled to a supply voltage node and a second terminal coupled to a collector terminal of the first transistor. A second transistor has an emitter terminal coupled to the collector terminal of the first transistor and a base terminal connected to the collector terminal of the second transistor. A second resistance has a first terminal coupled to the supply voltage node and a second terminal coupled to a collector terminal of the second transistor. A third transistor has a base terminal coupled to the base terminal of the second transistor, a collector terminal coupled to the supply voltage node, and an emitter terminal coupled to the output node.

Abstract: An improved phase-locked loop circuit includes a variable-frequency oscillator that generates a first oscillator signal, a reference signal source that generates a second oscillator signal, a control block that generates a select signal, and a frequency divider that receives as an input signal one of the first and second oscillator signals. The frequency divider also receives the select signal from the control block. The frequency divider generates a plurality of frequency-divided signals in response to the input signal, and passes through a selected one of the plurality of frequency-divided signals as an output signal in response to the select signal. The frequency divider also synchronizes its output signal to its input signal. The phase-locked loop also includes a frequency comparator that receives the output signal of the frequency divider and a signal derived from one of the first and second oscillator signals.

Abstract: A universal serial bus transceiver is disclosed. In one embodiment, the transceiver includes a differential transmitting amplifier with a first input terminal that receives a reference voltage, a second input terminal that receives a first data input signal at a level corresponding to the reference voltage, and a third input terminal that receives a second data input signal at the reference voltage level. The differential transmitting amplifier generates first and second bus data output signal at the bus signal level in response to the first and second data input signals. The transceiver also includes a first receiving amplifier with a first input terminal that receives the reference voltage and a second input terminal that receives a first bus data input signal at the bus signal level. The first receiving amplifier generates a first data output signal at the reference voltage level.

Abstract: An improved programmable logic device that generates output signals skewed in time includes a set of I/O cells and first and second logic circuits. Each logic circuit generates a logic output signal on a respective output line coupled to at least one of the I/O cells. A first delay element coupled to the output line of the first logic circuit is programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to a first delay control signal. A second delay element coupled to the output line of the second logic circuit is programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal. Control circuitry generates the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits.

Abstract: A method for minimizing instantaneous currents ina signal bus is disclosed. The method involves providing a programmable delay element in each of the signal buffers driving the signal on the bus. The programmable delay element in each signal buffer is selectable enabled to include a predetermined time delay. The method involves programming the delay elements in a selected group of the signal buffers t includde the predetermined time delay, so that the selected group of signal buffers each generate an output signal switching after the predetermined delay relative to the switching of output signals generated by other signal buffers.

Abstract: An improved wafer polishing machine is disclosed. In one embodiment, the wafer polishing machine has a movable polishing surface and a holder that holds an object, such as a semiconductor wafer, against the movable polishing surface. The holder includes a support structure that supports the object in contact with the polishing surface and an annular retaining ring that retains the object in alignment with the support structure. The retaining ring has a plurality of projections projecting inwardly from its inner circumference. The projections are evenly spaced around the inner circumference of the retaining ring. In one embodiment, the projections on the retaining ring define a circle with a diameter no less than the diameter of the object being polished. In an alternative embodiment, the retaining ring has a smooth, circular inner circumference formed from a flexible material which distends to from a continuous arc of contact with the wafer during polishing.

Abstract: An electrostatic discharge protection device for reducing electrostatic discharge spikes on a signal line is disclosed. The electrostatic discharge protection device includes first and second contact regions formed in a semiconductor material such as a compound semiconductor substrate. A first terminal is electrically coupled between the signal line and the first contact region. A second terminal is electrically coupled between the second contact region and a sink such as ground. An isolation region is formed in the semiconductor material between the first and second contact regions. The isolation region may be an implant-damaged region of the semiconductor material. The electrostatic discharge protection device provides protection against electrostatic discharges for integrated circuit components, while adding only a small amount of parasitic capacitance to I/O lines, which is particularly important in RF signal processing circuitry.

Abstract: An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal.

Abstract: An RF power amplifier with variable bias current is disclosed. The RF amplifier includes a peak detector that detects the peak level of the amplifier input signal. The peak detector generates an output signal in response to the peak level of the amplifier input signal. A bias voltage level setting circuit coupled to the peak detector receives the peak detector output signal and generates a bias voltage in response to the peak detector output signal. An amplifier circuit coupled to the bias voltage level setting circuit receives the bias voltage and the amplifier input signal, and generates an output signal in response to the bias voltage and the amplifier input signal. The disclosed RF amplifier allows amplification of RF signals with high linearity and high efficiency at varying power levels, and extends the maximum power capability of the amplifier.

Abstract: Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.